Research Catalog
Formal semantics and proof techniques for optimizing VHDL models
- Title
- Formal semantics and proof techniques for optimizing VHDL models / Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey.
- Author
- Umamageswaran, Kothanda, 1974-
- Publication
- Boston : Kluwer Academic Publishers, c1999.
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| Status | Format | Access | Call Number | Item Location |
|---|---|---|---|---|
| Text | Request in advance | JSE 99-450 | Offsite |
Details
- Additional Authors
- Description
- xvi, 158 p. : ill.; 25 cm.
- Subject
- Bibliography (note)
- Includes bibliographical references (p. [151]-155) and index.
- Call Number
- JSE 99-450
- ISBN
- 0792383753 (alk. paper)
- LCCN
- 98045668
- OCLC
- vendor
- Author
- Umamageswaran, Kothanda, 1974-
- Title
- Formal semantics and proof techniques for optimizing VHDL models / Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey.
- Imprint
- Boston : Kluwer Academic Publishers, c1999.
- Bibliography
- Includes bibliographical references (p. [151]-155) and index.
- Added Author
- Pandey, Sheetanshu L., 1972-Wilsey, Philip A., 1958-
- Research Call Number
- JSE 99-450