Research Catalog

Title

Computer hardware description languages and their applications : proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL'93 sonsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993 / edited by David Agnew, Luc Calaesen, Raul Camposano.

Author

International Symposium on Computer Hardware Description Languages and Their Applications (11th : 1993 : Ottawa, Ont.)

Publication

Amsterdam ; London : North-Holland, 1993.

Items in the Library & Off-site

Holdings

Details

Additional Authors

• Agnew, David, 1947-
• Claesen, Luc J. M.
• Camposano, Raul.

Description

xiv, 604 pages : illustrations; 23 cm

Subject

• Computer hardware description languages > Congresses

Bibliography (note)

• Includes bibliographical references.

Contents

• "Real Time Distributed Systems (invited presentation)" / Mario R. Barbacci -- "Verification of the Futurebus+ Cache Coherence Protocol" / E. M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D. E. Long, K. L. McMillan and L. A. Ness -- "Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation" / P. Camurati, F. Corno and P. Prinetto -- "Hardware-Verification using First Order BDDs" / K. Schneider, R. Kumar and T. Kropf -- "HW/SW Co-Design with PRAMs Using CoDES" / K. Buchenrieder, A. Sedlmeier and C. Veith -- "Prevail-DM: A Framework-Based Environment for Formal Hardware Verification" / F. R. Wagner -- "Better Verification Through Symmetry" / C. N. Ip and D. L. Dill -- "A Rewriting Based Method for the Formal Verification of Microprocessors" / M. Allemand -- "Reasoning about the VHDL Standard Logic Package Signal Data Type" / J. W. Gambles and P. J. Windley.
• "An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area" / X.-J. Xu and M. Ishizuka -- "Integrating Boolean Verification with Formal Derivation" / B. Bose, S. D. Johnson and S. Pullela -- "Automated High-level Verification Against Clocked Algorithmic Specifications" / F. Corella -- "The Backward Walk Approach in FSM Verification" / S. Krischer -- "Automatic Verification of Sequential Circuit Designs (invited presentation.)" / Edmund M. Clarke -- "Toward a Basis for Protocol Specification and Process Decomposition" / K. Rath and S. D. Johnson -- "Integrating SDL and VHDL for System-Level Hardware Design" / W. Glunz, T. Kruse, T. Rossel and D. Monjau -- "Reasoning About Array Structures Using a Dependently Typed Logic" / A. Dent and K. Hanna -- "VHDL Description and Formal Verification of Systolic Multipliers" / L. Pierre -- "Transformational Rewriting with Ruby" / R. Sharp and O. Rasmussen.
• "A Representation for the Binding of RT-Component Functionality to HDL Behavior" / R. P. Ang and N. D. Dutt -- "Performance Specification and Measurement" / R. Mandayam and R. Vemuri -- "Automatic Synthesis of Sequential Synchronizations" / Z. Zhu and S. D. Johnson -- "Specifying Hardware Systems in LOTOS" / M. Faci and L. Logrippo -- "HML: A Hardware Description Language Based on Standard ML" / J. O'Leary, M. Linderman, M. Leeser and M. Aagaard -- "An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems" / B. Selic -- "Linking System Design Tools and Hardware Design Tools" / A. A. Jerraya, K. O'Brien and T. Ben Ismail -- "Automatic VHDL Model Generation System" / S. Kang and S. A. Szygenda -- "The Modeler's Assistant: A CAD Tool for Behavioral Model Development" / R. Singh, J. Wicks, P. Wright and J. R. Armstrong -- "Insulin: An Instruction Set Simulation Environment" / S. Sutarwala, P. G. Paulin and Y. Kumar.
• "Specification languages for communication protocols (invited presentation)" / Gregor v. Bochmann -- "Integrating Behavior and Timing in Executable Specifications" / K. Khordoc, M. Dufresne, E. Cerny, P. A. Babkine and A. Silburt -- "ESP: An Executable Specification Language for Mixed Timing Control Circuits" / T.-A. Chu, H. T. Cao and C. K. C. Leung -- "UDL/I version Two: A New Horizon of HDL Standards" / T. Hoshino -- "Verilog HDL Modeling Styles for Formal Verification" / F. Balarin and G. York -- "A Visual Hardware Description Language" / E. J. Golin and A. C. Feng -- "Textual/Graphical Design Concept-Level Synthesis" / W. R. Cyre -- "System-Level Specification and Design Using VHDL: A Case Study" / W. Ecker and S. Marz -- "A Denotational Definition of the VHDL Simulation Kernel" / K. C. Davis -- "Checking DFT Rules with a VHDL Simulator" / W. Glunz and T. Rossel -- "Parameterized VHDL entities for the simulation of hybrid circuits" / M. Ryba, W. Seibold, U. G. Baitinger and U. Thelen.
• "Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models" / Z. Navabi, A. Hashemi, M. Eghtesad and M. Vai -- "Analog-VHDL: As an application, a real example" / D. Rodriguez.

ISBN

0444816410 (pbk) :

LCCN

gb 93057094

OCLC

ocm29358497

Owning Institutions

Columbia University Libraries