Research Catalog

Title

Proceedings of the International Conference on Application Specific Array Processors : August 22-24, 1994, San Francisco, California / sponsored by IEEE Computer Society Technical Committee on VLSI ; edited by Peter Cappello, et. al.

Author

International Conference on Application Specific Array Processors (8th : 1994 : San Francisco, Calif.)

Publication

Los Alamitos, Calif. : IEEE Computer Society Press, 1994.

Items in the Library & Off-site

Details

Additional Authors

• Cappello, Peter R.
• IEEE Computer Society.
• IEEE Computer Society. Technical Committee on VLSI.

Description

xii, 452 pages : illustrations; 24 cm

Alternative Title

Application specific array processors.

Subject

• Application-specific integrated circuits > Congresses
• Array processors > Congresses

Note

• IEEE Catalog Number 94TH0687-4.

Bibliography (note)

• Includes bibliographical references and index.

Contents

• Cellular Neural Network Universal Machine: An Analogic Supercomputer on a Chip / L. O. Chua -- Fast Linear Hough Transform / J. E. Vuillemin -- Algorithms and Architectures for Hierarchical Compression of Video / M. Vishwanath -- A High Performance IIR Filter Chip and its Evaluation System / R. L. Walke, R. A. Evans, R. F. Woods, G. Floyd and K. W. Wood -- Automated Design of DSP Array Processor Chips / J. V. McCanny, Y. Hu and M. Yan -- Behavioral Synthesis of High Performance, Low Cost, and Low Power Application Specific Processors for Linear Computations / M. Potkonjak and M. B. Srivastava -- Distributed Control Synthesis for Data-Dependent Iterative Algorithms / B. Jung, Y. Jeong and W. P. Burleson -- Rapid Prototyping with Programmable Control Paths / R. S. Bajwa, C. Nagendra, P. Keltcher and M. J. Irwin -- Minimizing Memory Requirements in Rate-Optimal Schedules / R. Govindarajan, G. R. Gao and P. Desai.
• A Methodology for Performance Prediction of Sphinx I in Multi-Computer Architectures / C. Hernandez, D. Siewiorek and Z. Segall -- Optimal Synthesis of Application Specific Heterogenous Pipelined Multiprocessors / J. C. DeSouza-Batista and A. C. Parker -- Register Transfer Modeling and Simulation for Array Processors / W. H. Chou and S. Y. Kung -- A Systolic Array for 2-D DFT and 2-D DCT / H. Lim and E. E. Swartzlander, Jr. -- Analog VLSI Arrays for Morphological Image Processing / T. G. Morris and S. P. DeWeerth -- A Fast Pipelined FFT Unit / L. Breveglieri and V. Piuri -- Parallel Architectures for Computing the Hough Transform and CT Image Reconstruction / L. Lin and V. K. Jain -- Verification of Regular Architectures Using ALPHA: A Case Study / C. Dezan and P. Quinton -- A Processor-Time-Minimal Schedule for the Standard Tensor Product Algorithm / C. Scheiman and P. Cappello -- A Processor for Calorimetry at the Large Hadron Collider in the FERMI Project / L. Dadda, S. Inkinen and V. Piuri.
• Regular Array Synthesis Using ALPHA / D. K. Wilde and O. Sie -- Data Compiling for Systems for Affine Recurrence Equations / C. Mongenet -- Optimal Mapping of Systolic Algorithms by Regular Instruction Shifts / P. Clauss and G.-R. Perrin -- On the Injectivity of Modular Mappings / H. J. Lee and J. A. B. Fortes -- A Variable-Precision Interval Arithmetic Processor / M. J. Schulte and E. E. Swartzlander, Jr. -- Architectures for Lattice Structure Based Orthonormal Discrete Wavelet Transforms / T. C. Denk and K. K. Parhi -- A Data Path Array with Shared Memory as Core of a High Performance DSP / J. Kneip, K. Ronner and P. Pirsch -- Synthesis of a Class of Data Format Converters with Specified Delays / J. Bae, V. K. Prasanna and H. Park -- Designing Systolic Arrays for Integer GCD Computation / T. Jebelean -- A Sparse Knapsack Algo-tech-cuit and its Synthesis / R. Andonov and S. Rajopadhye.
• A Parallel System for Photo-Realistic Artificial Scene Rendering / E. F. Deprettere, G. H. Hekstra, L.-S. Sheng, J. Bu and G. Boersma -- Parallel Processing of Complex Data Using Quaternion and Pseudo-Quaternion CORDIC Algorithms / S.-F. Hsiao and J.-M. Delosme -- A SIMD Solution to the Sequence Comparison Problem on the MGAP / M. Borah, R. S. Bajwa, S. Hannenhalli and M. J. Irwin -- Access and Alignment of Arrays for a Bidimensional Parallel Memory / C. Verdier, E. Boutillon, A. Lafage and A. Demeure -- Constant-Time Triangulation Problems on Reconfigurable Meshes / V. Bokka, H. Gurla, S. Olariu and J. L. Schwing -- A Scalable Bit-Sequential SIMD Array for Nearest-Neighbor Classification Using the City-Block Metric / M. Neschen -- A Parallel DSP-Based Neural Network Emulator with CMOS VLSI Packet Switching Hardware / M. Schwartz, B. J. Hosticka, M. Kesper, P. Richert and M. Scholles -- An Efficient VLSI Architecture for Digital Geometry / R. Lin, S. Olariu and J. L. Schwing.
• A Dynamically Reconfigurable Wavefront Array Architecture for Evaluation of Expressions / R. W. Hartenstein, R. Kress and H. Reinig -- An Optimisation Methodology for Array Mapping of Affine Recurrence Equations in Video and Image Processing / J. Rosseel, F. Catthoor and H. De Man -- Loop Transformation Methodology for Fixed-Rate Video, Image and Telecom Processing Applications / F. Catthoor, W. Geurts and H. De Man -- Data Alignment of Loop Nests without Nonlocal Communications / W. Shang and Z. Shu.

ISBN

• 0818665173 (case)
• 0818665165 (microfiche)

OCLC

ocm31138496

Owning Institutions

Columbia University Libraries