Research Catalog

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems : November 3-5, 1994, Salt Lake City, Utah

Title
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems : November 3-5, 1994, Salt Lake City, Utah / sponsored by IEEE Computer Society Technical Committee on VLSI, in cooperation with the National Science Foundation [and] IFIP Working Groups 10.2 and 10.5 ; [general co-chairs, Erik Brunvand, Alan Davis].
Author
International Symposium on Advanced Research in Asynchronous Circuits and Systems (1994 : Salt Lake City, Utah)
Publication
Los Alamitos, California : IEEE Computer Society Press, [1994], ©1994.

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Details

Additional Authors
  • Brunvand, Erik.
  • Davis, W. Alan.
  • IEEE Computer Society. Technical Committee on VLSI.
  • National Science Foundation (U.S.)
  • IFIP WG 10.2.
  • IFIP WG 10.5.
Description
xii, 258 pages : illustrations; 28 cm
Alternative Title
  • Advanced research in asynchronous circuits and systems.
  • Async94.
Subject
  • Asynchronous circuits > Design and construction > Congresses
  • Switching circuits > Design and construction > Congresses
  • Asynchronous transfer mode > Congresses
  • Digital electronics > Congresses
  • Electronic circuit design > Congresses
  • Logic design > Congresses
  • Asynchronous circuits > Automation > Congresses
Note
  • "Async94"--P. ix.
  • "IEEE Computer Society Press order number 6210-02"--T.p. verso.
  • "IEEE catalog number 94TH06627"--T.p. verso.
Bibliography (note)
  • Includes bibliographical references and index.
Contents
  • Bounded Delay Timing Analysis of a Class of CSP Programs with Choice / H. Hulgaard and S. M. Burns -- Tools for Validating Asynchronous Digital Circuits / A. Ashkinazy, D. Edwards, C. Farnsworth, G. Gendel and S. Sikand -- Timing-Reliability Evaluation of Asynchronous Circuits Based on Different Delay Models / M. Kuwako and T. Nanya -- Sufficient Conditions for Correct Gate-Level Speed-Independent Circuits / P. A. Beerel, J. R. Burch and T. H.-Y. Meng -- Characterizing Speed-Independence of High-Level Designs / M. Kishinevsky and J. Staunstrup -- Retargeting a Hardware Compiler Proof Using Protocol Converters / G. Brown, W. Luk and J. O'Leary -- Verification of the Speed-Independent Circuits by STG Unfoldings / A. Kondratyev and A. Taubin -- How Fast Will the Flip Flop? / M. R. Greenstreet and P. Cahoon -- Pipeline Synchronization / J. N. Seizovic -- Metastable-Robust Self-Timed Circuit Synthesis from Live Safe Simple Signal Transition Graphs / E. C. Y. Chung and L. Kleeman.
  • Designing Asynchronous Circuits from Behavioral Specifications with Internal Conflicts / J. Cortadella, L. Lavagno, P. Vanbekbergen and A. Yakovlev -- Performance Comparison of Asynchronous Adders / M. A. Franklin and T. Pan -- An Asynchronous Pipelined Lattice Structure Filter / U. V. Cummings, A. M. Lines and A. J. Martin -- Building Fast Bundled Data Circuits with a Specialized Standard Cell Library / P. T. Roine -- An Event Controlled Reconfigurable Multi-Chip FFT / S. V. Morton, S. S. Appleton and M. J. Liebelt -- A Delay-Controlled Phase-Looked Loop to Reduce Timing Errors in Synchronous/Asynchronous Communication Links / J. F. Chappel and S. G. Zaky -- A Technique for Estimating Power in Asynchronous Circuits / P. Kudva and V. Akella -- Low-Energy Asynchronous Memory Design / J. A. Tierno and A. J. Martin -- Utilising Dynamic Logic for Low Power Consumption in Asynchronous Circuits / C. Farnsworth, D. A. Edwards and S. S. Sikand.
  • Efficient Building Blocks for Delay Insensitive Circuits / P. Patra and D. S. Fussel -- Formal Design of an Asynchronous DSP Counterflow Pipeline: A Case Study in Handshake Algebra / M. B. Josephs, P. G. Lucassen, J. T. Udding and T. Verhoeff -- Composable Specifications for Asynchronous Systems Using UNITY / M. Bickford -- Delay-Insensitive Solutions to the Committee Problem / I. Benko and J. C. Ebergen -- Testing Micropipelines / A. Khoche and E. Brunvand -- Partial Scan Test for Asynchronous Circuits Illustrated on a DCC Error Corrector / M. Roncken -- The Counterflow Pipeline Processor / Ivan Sutherland, Robert Sproull, Dave Roberts, Charles Molnar, Ian Jones, Bill Coates, Robert Yung and John Lexau.
ISBN
  • 0818662107 (paper)
  • 0818662115 (microfiche)
OCLC
  • 31762561
  • ocm31762561
Owning Institutions
Columbia University Libraries