Research Catalog
Formal semantics for VHDL
- Title
- Formal semantics for VHDL / edited by Carlos Delgado Kloos and Peter T. Breuer.
- Publication
- Boston : Kluwer Academic Publishers, [1995], ©1995.
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| Status | Format | Access | Call Number | Item Location |
|---|---|---|---|---|
| Text | Request in advance | TK885.7 .F67 1995 | Off-site |
Holdings
Details
- Additional Authors
- Description
- xiv, 249 pages : illustrations; 25 cm.
- Summary
- It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several commercially- and academically-based tools.
- Having different tools and users generating and reading the same language requires that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English.
- But rigor and clarity is very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations.
- Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras.
- Formal Semantics for VHDL is essential reading for researchers in Formal Methods and can be used as a text for an advanced course on the subject.
- Series Statement
- The Kluwer international series in engineering and computer science. VLSI, computer architecture and digital signal processing
- Uniform Title
- Kluwer international series in engineering and computer science. VLSI, computer architecture, and digital signal processing.
- Subject
- Bibliography (note)
- Includes bibliographical references (p. 239-249).
- Contents
- 0. Giving Semantics to VHDL: An Introduction / Carlos Delgado Kloos and Peter T. Breuer -- 1. A Functional Semantics for Delta-Delay VHDL Based on Focus / Max Fuchs and Michael Mendler -- 2. A Functional Semantics for Unit-Delay VHDL / Peter T. Breuer, Luis Sanchez Fernandez and Carlos Delgado Kloos -- 3. An Operational Semantics for a Subset of VHDL / John P. Van Tassel -- 4. A Formal Definition of an Abstract VHDL'93 Simulator by EA-Machines / Egon Borger, Uwe Glasser and Wolfgang Muller -- 5. A Formal Model of VHDL Using Coloured Petri Nets / Serafin Olcoz -- 6. A Deterministic Finite-State Model for VHDL / Gert Dohmen and Ronald Herrmann -- 7. A Flow Graph Semantics of VHDL: A Basis for Hardware Verification with VHDL / Ralf Reetz and Thomas Kropf.
- ISBN
- 0792395522 (acid-free paper)
- LCCN
- 94046912
- OCLC
- 31754880
- ocm31754880
- Owning Institutions
- Columbia University Libraries