Research Catalog

Title

Proceedings of the Eighth International Symposium on System Synthesis, September 13-15, 1995, Cannes, France / sponsored by The IEEE Computer Society Technical Committee on Design automation, The ACM Special Interest Group on Design Automation ; in cooperation with IFIP Workgroup 10.25 ; with corporate support by SGS-Thomson Microelectronics, France Telecom, TIMA/CNRS-INPG-UJF.

Author

International Symposium on System Synthesis (8th : 1995 : Cannes, France)

Publication

Los Alamitos, Calif. : IEEE Computer Society Press, [1995], ©1995.

Items in the Library & Off-site

Holdings

Details

Additional Authors

• IEEE Computer Society. Design Automation Technical Committee.
• ACM Special Interest Group on Design Automation.

Description

xiii, 175 pages; 28 cm

Alternative Title

• Eighth International Symposium on System Synthesis
• System Synthesis

Subjects

• System design > Congresses
• Systems software > Congresses
• Operating systems (Computers) > Congresses
• Computer-aided software engineering > Congresses

Note

• "IEEE catalog number 95TH8050"--T.p. verso.
• "IEEE Computer Society Press Order Number PR07076"--T.p. verso.
• "ACM Order Number 481950"--T.p.

Bibliography (note)

• Includes bibliographical references (p. 174) and index.

Contents

• Invited Talk: Multimedia: A New Design Challenge for Systems-On-Silicon / H. Holzapfel -- Sensitivity-Driven Co-Synthesis of Distributed Embedded Systems / T.-Y. Yen and W. Wolf -- Multiple-Process Behavioral Synthesis for Mixed Hardware/Software Systems / J. K. Adams and D. E. Thomas -- An Approach to Interface Synthesis / J. Madsen and B. Hald -- The Chinook Hardware/Software Co-Synthesis System / P. H. Chou, R. B. Ortega and G. Borriello -- Clustering for Improved System-Level Functional Partitioning / F. Vahid and D. D. Gajski -- Optimal Code Generation for Embedded Memory Non-Homogeneous Register Architectures / G. Araujo and S. Malik -- Optimal Register Assignment to Loops for Embedded Code Generation / D. J. Kolson, A. Nicolau, N. Dutt and K. Kennedy -- Real-Time Multi-Tasking in Software Synthesis for Information Processing Systems / F. Thoen, M. Cornero, G. Goossens and H. De Man -- Time-Constrained Code Compaction for DSPs / R. Leupers and P. Marwedel --
• Industrial Experience Using Rule-Driven Retargetable Code Generation for Multimedia Applications / C. Liem, P. Paulin, M. Cornero and A. Jerraya -- Invited Talk: Real-Time Systems Specification and Verification / J. Sifakis -- Synthesis of Pipelined DSP Accelerators with Dynamic Scheduling / P. Schaumont, B. Vanthournout, I. Bolsens and H. De Man -- An Exact Methodology for Scheduling in a 3D Design Space / S. Chaudhuri, S. A. Blythe and R. A. Walker -- Procedure Exlining: A Transformation for Improved System and Behavioral Synthesis / F. Vahid -- Array Mapping in Behavioral Synthesis / H. Schmit and D. E. Thomas -- On the Use of VHDL-Based Behavioral Synthesis for Telecom ASIC Design / M. Genoe, P. Vanoostende and G. Van Wauwe -- Scheduling and Resource Binding for Low Power / E. Musoll and J. Cortadella -- Power Analysis and Low-Power Scheduling Techniques for Embedded DSP Software / M. T.-C. Lee, V. Tiwari, S. Malik and M. Fujita --
• A Path-Based Technique for Estimating Hardware Runtime in HW/SW-Cosynthesis / J. Henkel and R. Ernst -- A Comprehensive Estimation Technique for High-Level Synthesis / S. Y. Ohm, F. J. Kurdahi, N. Dutt and M. Xu -- Profiling in the ASP Codesign Environment / M. F. Parkinson and S. Parameswaran -- WWW Based Structuring of Codesigns / P. G. Ploger, J. Wilberg, M. Langevin and R. Camposano -- System Level Verification of Video and Image Processing Specifications / H. Samsom, F. Franssen, F. Catthoor and H. De Man -- Synthesis of System-Level Communication by an Allocation-Based Approach / J.-M. Daveau, T. Ben Ismail and A. A. Jerraya -- Modeling and Simulation of Heterogeneous Real-Time Systems Based on a Deterministic Discrete Event Model / J. Teich, L. Thiele and E. A. Lee -- A System Level Design Methodology for the Optimization of Heterogeneous Multiprocessors / M. Schweigershausen and P. Pirsch -- 1995 High Level Synthesis Design Repository / P. R. Panda and N. D. Dutt.

ISBN

• 0897917715 (ACM : paper)
• 0818670762 (IEEE : paper)
• 0780325281 (IEEE : microfiche)

OCLC

ocm34147083

Owning Institutions

Columbia University Libraries