Research Catalog

Title

Sixteenth Conference on Advanced Research in VLSI : proceedings : March 27-29, 1995, Chapel Hill, North Carolina / sponsored by University of North Carolina, Chapel Hill, Massachusetts Institute of Technology in cooperation with IEEE Computer Society ; edited by William J. Dally, John W. Poulton, Alexander T. Ishii.

Author

Conference on Advanced Research in VLSI (16th : 1995 : Chapel Hill, N.C.)

Publication

Los Alamitos, Calif. : IEEE Computer Society Press, [1995], ©1995.

Items in the Library & Off-site

Holdings

Details

Additional Authors

• Dally, William J.
• Poulton, John W.
• Ishii, Alexander T.
• Massachusetts Institute of Technology.
• University of North Carolina at Chapel Hill.
• IEEE Computer Society.

Description

x, 448 pages : illustrations; 24 cm

Subject

• Integrated circuits > Very large scale integration > Research > Congresses

Bibliography (note)

• Includes bibliographical references and index.

Contents

• CAD for Embedded System Design / Kurt Keutzer -- Combined DRAM and Logic Chip for Massively Parallel Systems / P. M. Kogge, T. Sunaga, H. Miyataka, K. Kitamura and E. Retter -- Silicon VLSI Processing Architectures Incorporating Integrated Optoelectronic Devices / H. H. Cat, M. Lee, B. Buchanan, D. S. Wills, M. Brooke and N. M. Jokerst -- Abacus: A 1024 Processor 8 ns SIMD Array / M. Bolotski, T. Simon, C. Vieri, R. Amirtharajah and T. F. Knight, Jr. -- Automatic Synthesis of Gate-Level Timed Circuits with Choice / C. J. Myers, T. G. Rokicki and T. H.-Y. Meng -- Algorithms for the Optimal State Assignment of Asynchronous State Machines / R. M. Fuhrer, B. Lin and S. M. Nowick -- Low Latency Self-Timed Flow-Through FIFOs / E. Brunvand -- High Speed Counterflow-Clocked Pipelining Illustrated on the Design of HDTV Subband Vector Quantizer Chips / J.-T. Yoo, G. Gopalakrishnan, K. F. Smith and V. J. Mathews -- Bit-Serial Bidirectional A/D/A Conversion / G. Cauwenberghs --
• Dynamic CMOS Circuit Techniques for Delay and Power Reduction in Parallel Adders / H. Lindkvist and P. Andersson -- A Technique for High-Speed, Fine-Resolution Pattern Generation and its CMOS Implementation / G. C. Moyer, M. Clements, W. Liu, T. Schaffer and R. K. Cavin III -- Rapid Single-Flux-Quantum Logic: A New Family of Ultrafast Superconductor Digital Circuits / Konstantin K. Likharev -- Array-of-Arrays Architecture for Parallel Floating Point Multiplication / H. Dhanesha, K. Falakshahi and M. Horowitz -- A Multi-Sender Asynchronous Extension to the AER Protocol / J. Lazzaro and J. Wawrzynek -- Recursive Layout Generation / L. M. Monier, R. W. Haddad and J. Dion -- HAL: Heuristic Algorithms for Layout Synthesis / S. Rekhi and J. D. Trotter -- Efficient Galerkin Techniques for Multipole-Accelerated Capacitance Extraction of 3-D Structures with Multiple Dielectrics / X. Cai, K. Nabors and J. White --
• Standard CMOS Active Pixel Image Sensors for Multimedia Applications / A. Dickinson, B. Ackland, E.-S. Eid, D. Inglis and E. R. Fossum -- A 590,000 Transistor 48,000 Pixel, Contrast Sensitive, Edge Enhancing, CMOS Imager-Silicon Retina / A. G. Andreou and K. A. Boahen -- Analog VLSI Circuits for Manufacturing Inspection / T. G. Morris, D. M. Wilson and S. P. DeWeerth -- OPTIMUS: A New Program for OPTIMizing Linear Circuits with Number-Splitting and Shift-and-Add Decompositions / H. Nguyen and A. Chatterjee -- Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques / S. Y. Liao, S. Devadas and K. Keutzer -- Systematic Objective-Driven Computer Architecture Optimization / T. J. Stanley and T. Mudge -- Design of Low-Power Portable Systems / Anantha P. Chandrakasan -- Low-Latency Plesiochronous Data Retiming / L. R. Dennison, W. J. Dally and D. Xanthopoulos -- Distributed Synchronous Clocking / G. A. Pratt and J. Nguyen --
• Single-Transistor Transparent-Latch Clocking / K.-Y. Khoo and A. N. Willson, Jr. -- On the Performance of Level-Clocked Circuits / C. Ebeling and B. Lockyear -- Quasi-Algebraic Decompositions of Switching Functions / T. Stanion and C. Sechen -- Efficient Retiming under a General Delay Model / K. N. Lalgudi and M. C. Papaefthymiou -- An Evaluation of Bipartitioning Techniques / S. Hauck and G. Borriello -- Non-Dissipative Rail Drivers for Adiabatic Circuits / S. G. Younis and T. F. Knight, Jr. -- Energy Recovery for Low-Power CMOS / W. C. Athas and N. Tzartzanis -- Optimization of Combinational and Sequential Logic Circuits for Low Power Using Precomputation / J. Monteiro, J. Rinderknecht, S. Devadas and A. Ghosh -- 3-Dimensional Packaging for VLSI Systems / Howard L. Davidson -- Previous ARVLSI Proceedings.

ISBN

0818670479

LCCN

94073539

OCLC

• 32511825
• ocm32511825

Owning Institutions

Columbia University Libraries