Research Catalog

Title

Proceedings, the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, November 13-15, 1995, Lafayette, Louisiana / sponsored by the IEEE Computer Society, the IEEE Computer Society Technical Committee on Fault-Tolerant Computing.

Author

International Workshop on Defect and Fault Tolerance in VLSI Systems (1995 : Lafayette, La.)

Publication

Los Alamitos, Calif. : IEEE Computer Society Press, [1995], ©1995.

Items in the Library & Off-site

Details

Additional Authors

• IEEE Computer Society.
• IEEE Computer Society. Fault-Tolerant Computing Technical Committee.

Description

x, 305 pages : illustrations; 24 cm

Subjects

• Fault-tolerant computing > Congresses
• Integrated circuits > Very large scale integration > Design and construction > Congresses

Note

• "IEEE Computer Society Press Order Number PR07107"--T.p. verso.
• "IEEE Order Plan Catalog Number 95TB100009"--T.p. verso.
• "ISSN 1063-6722"--T.p. verso.

Bibliography (note)

• Includes bibliographical references and index.

Contents

• Approximation of Critical Area of ICs with Simple Parameters Extracted from the Layout / F. Duvivier and M. Rivier -- AFFCCA: A Tool for Critical Area Analysis with Circular Defects and Lithography Deformed Layout / W. Maly, I. Bubel, T. Waas, P. K. Nag, H. Hartmann, D. Schmitt-Landsiedel and S. Griep -- Hierarchical Extraction of Critical Area for Shorts in Very Large Ics / P. K. Nag and W. Maly -- Hierarchical Critical Area Extraction with the EYE tool / G. A. Allan and A. J. Walton -- Wafer-Scale Integration Defect Avoidance Tradeoffs between Laser Links and Omega Network Switching / G. H. Chapman, D. E. Bergen and K. Fang -- The Effect of Spot Defects on the Parametric Yield of Long Interconnection Lines / I. A. Wagner and I. Koren -- Critical Area Extraction of Extra Material Soft Faults / G. A. Allan and A. J. Walton -- Switch Level Hot-Carrier Reliability Enhancement of VLSI Circuits / R. Karri and A. Dasgupta --
• A Model for the Evaluation of Fault Tolerance in the FERMI System / L. Breveglieri and A. Antola -- Efficient Algorithms for Analyzing and Synthesizing Fault-Tolerant Datapaths / S. S. Ravi, R. Narasimhan and D. J. Rosenkrantz -- Bit-Modular Defect/Fault-Tolerant Convolvers / L. Dadda and V. Piuri -- A Channel-Constrained Reconfiguration Approach for Processing Arrays / M. Sami, F. Distante and R. Stefanelli -- Reconfigurable Architectures for Mesh-Arrays with PE and Link Faults / I. Takanami and T. Horita -- Totally Defect-Tolerant Arrays Capable of Quick Broadcasting / N. Tsuda, T. Ishikawa and Y. Nakamura -- ADTS: An Array Defect-Tolerance Scheme for Wafer Scale Gate Arrays / A. D. Singh -- An Improved Approach to Fault Tolerant Rank Order Filtering on a SIMD Mesh Processor / J.-H. Kim, F. Lombardi and N. H. Vaidya -- Yield Projection from Defect Monitors: The Influence of Gross Defects / N. Harrison --
• Accurate Yield Estimation of Circuits with Redundancy / D. Gaitonde, D. M. H. Walker and W. Maly -- Using Defect Density Modelling to Drive the Optimization of Circuit Layout, Maximizing Yield / M. Baxter and D. Muir -- Layer Assignment for Yield Enhancement / Z. Chen and I. Koren -- Analyzing and Improving Delay Defect Tolerance in Pipelined Combinatorial Circuits / D. Wessels and J. C. Muzio -- Cost Analysis of a New Algorithmic-Based Soft-Error Tolerant Architecture / Y. Blaquiere, G. Gagne, Y. Savaria and C. Evequoz -- Efficient Time Redundancy for Error Correcting Inner-Product Units and Convolvers / E. Swartzlander, Y. M. Hsu and V. Piuri -- A Study of Time Redundant Fault Tolerance Techniques for Superscalar Processors / M. Franklin -- Repair Algorithms for Mirrored Disk Systems / F. Lombardi, H. H. Kari, H. Saikkonen and S. S. Kim -- A Row-Based FPGA for Single and Multiple Stuck-at Fault Detection / X. Sun, X. T. Chen, W. K. Huang and F. Lombardi --
• Utilizing Spares in Multichip Modules for the Dual Function of Fault Coverage and Fault Diagnosis / S. Goldberg and S. J. Upadhyaya -- FFT-based Test of a Yield Monitor Circuit / C. Thibeault and A. Payeur -- Design of Defect-Tolerant Scan Chains for MCMs with an Active Substrate / R. Leveugle, P. Brahic and G. Saucier -- Characterization and Analysis of Errors in Circuit Test / E. Swartzlander and T. Ziaja -- Self-checking FSMs Based on a Constant Distance State Encoding / D. Sciuto, C. Bolchini, R. Montandon and F. Salice -- Construction of the SbEC-DbED and DbEC Codes, and their Applications / S. Xiao, G. L. Feng, X. Shi and T. R. N. Rao -- Novel Berger Code Checker / C. Metra, M. Favalli and B. Ricco -- Single Fault Masking Logic Designs with Error Correcting Codes / J.-C. Lo.

ISBN

• 0818671076
• 0818673826 (microfiche)

OCLC

ocm34058046

Owning Institutions

Columbia University Libraries