Research Catalog

Title

Proceedings of the Seventh International Symposium on High-Level Synthesis : May 18-20, 1994, Niagara-on-the-Lake, Ontario, Canada / sponsored by the IEEE Computer Society Technical Committee on Design Automation, the Association for Computing Machinery Special Interest Group on Design Automation (SIGDA) ; in cooperation with IFIP Workgroups 10.2 and 10.5.

Author

International Symposium on High-Level Synthesis (7th : 1994 : Niagara-on-the-Lake, Ont.)

Publication

Los Alamitos, Calif. : IEEE Computer Society Press, [1994], ©1994.

Items in the Library & Off-site

Holdings

Details

Additional Authors

• IEEE Computer Society. Design Automation Technical Committee.
• ACM Special Interest Group on Design Automation.

Description

ix, 171 pages : illustrations; 28 cm

Alternative Title

7th International Symposium on High-Level Synthesis.

Subjects

• Computer-aided design > Congresses
• System design > Congresses

Note

• Spine title: 7th International Symposium on High-Level Synthesis.
• "IEEE Computer Society Press order number 5785-02"--T.p. verso.
• "IEEE catalog number 94TH0641-1"--T.p. verso.

Bibliography (note)

• Includes bibliographical references and index.

Contents

• Invited Talk: Hardware/Software Co-Verification in ATM / Giovanni Mancini -- A Methodology for Simulation and Synthesis of Mixed Hardware/Software Systems (talk only) / A. Kalavade and E. A. Lee -- Instruction Set Definition and Instruction Selection for ASIPs / J. Van Praet, G. Goossens, D. Lanneer and H. De Man -- Data Routing: A Paradigm for Efficient Data-Path Synthesis and Code Generation / D. Lanneer, M. Cornero, G. Goossens and H. De Man -- Timing Analysis for Synthesis in Microprocessor Interface Design / M. A. Escalante and N. J. Dimopoulos -- Applications of Attributed-Behavior Synthesis / L. F. Arnstein and D. Thomas -- Computing Lower Bounds on Functional Units before Scheduling / S. Chaudhuri and R. A. Walker -- Timing Estimation for Behavioral Descriptions / D. Mintz and C. Dangelo -- Efficient Timing Constraint Derivation for Optimal Retiming High Speed Processing Units / A. van der Werf, J. L. Van Meerbergen, E. H. L. Aarts, W. F. J. Verhaegh and P. E. R. Lippens --
• SMASH: A Program for Scheduling Memory-Intensive Application-Specific Hardware / P. Gupta and A. C. Parker -- Ensemble Representation and Techniques for Exact Control-Dependent Scheduling / I. Radivojevic and F. Brewer -- Panel Session: Is High-Level Synthesis Marketable? -- Invited Talk: State-of-the-Art Compiler Optimization / Kenneth Zadeck -- An Integrated Approach to Retargetable Code Generation / T. Wilson, G. Grewal, B. Halley and D. Banerji -- Bit-Alignment for Retargetable Code Generators / K. Schoofs, G. Goossens and H. De Man -- Code Generation for a DSP Processor / W.-K. Cheng and Y.-L. Lin -- Retargetable Assembly Code Generation by Bootstrapping / R. Leupers, W. Schenk and P. Marwedel -- CodeSyn: A Retargetable Code Synthesis System (talk only) / P. G. Paulin, C. Liem, T. C. May and S. Sutarwala -- Concurrent Testing in High-Level Synthesis / R. Singh and J. Knight --
• Testing Two-Phase Transition Signaling Based Self-Timed Circuits in a Synthesis Environment / P. Kudva and V. Akella -- A Hybrid Numeric/Symbolic Program for Checking Functional and Timing Compatibility of Synthesized Designs / C.-T. Chen and A. C. Parker -- A Divide-and-Conquer Approach for Asynchronous Interface Synthesis / R. Puri and J. Gu -- Rapid Prototyping of Fault-Tolerant VLSI Systems / R. Karri, K. Hogstedt and A. Orailoglu -- Panel Session: ASICs vs ASIPs -- Specification of Interface Components for Synchronous Data Paths / P. Gutberlet and W. Rosenstiel -- Global Node Reduction of Linear Systems Using Ratio Analysis / M. Sheliga and E. H.-M. Sha -- A Specification Invariant Technique for Operation Cost Minimisation in Flow-Graphs / M. Janssen, F. Catthoor and H. De Man -- Controller and Datapath Trade-Offs in Hierarchical RT-Level Synthesis / D. S. Rao and F. J. Kurdahi -- How Datapath Allocation Affects Controller Delay / S. C.-Y. Huang and W. H. Wolf --
• An Algorithm for the Allocation of Functional Units from Realistic RT Component Libraries / R. Ang and N. Dutt.

ISBN

• 0818657855 (pbk.)
• 0818657863 (microfiche)

LCCN

94070059

OCLC

ocm30829771

Owning Institutions

Columbia University Libraries