Research Catalog

Title

VHDL International Users' Forum : proceedings : fall conference, October 19-22, 1997, Arlington, VA / sponsored by VHDL International, the IEEE Circuits & Systems Society ; in cooperation with Electronics Industries Association, European CAD Standards Initiative (ECSI).

Author

VHDL International. Users Forum (1997 : Arlington, Va.)

Publication

Los Alamitos, Calif. : IEEE Computer Society Press, [1997], ©1997.

Items in the Library & Off-site

Holdings

Details

Additional Authors

• IEEE Computer Society.
• VHDL International.
• IEEE Circuits and Systems Society.
• Electronic Industries Association.
• European CAD Standards Initiative (Firm)

Description

x, 279 pages : illustrations; 28 cm

Alternative Title

• VHDL International Users Forum
• VIUF'97
• Rapid systems prototyping with VHDL

Subjects

• VHDL (Computer hardware description language) > Congresses
• Electronic circuit design > Data processing > Congresses

Note

• "IEEE Computer Society order number PR08180"--T.p. verso.
• "IEEE order plan catalog number 97TB100191"--T.p. verso.

Bibliography (note)

• Includes bibliographical references and index.

Contents

• Implementing a Complete Test Tool Set in VHDL / A. Peymandoust and Z. Navabi -- Using WAVES for Verification of Synthesized Sub-Components in a Deeply Hierarchical Design / B. Kadrovach, P. Jarusiewic and B. Read [et al.] -- Functional Fault Simulation of VHDL Gate Level Models / S. Aftabjahani and Z. Navabi -- Mixed-Level Modeling in VHDL using the Watch-and-React Interface / W. Dungan, R. Klenke and J. Aylor -- A Performance Modeling Framework Applied to Real Time Infrared Search and Tract Processing / E. Pauer, M. Pettigrew and C. Myers [et al.] -- Rapid-Prototyping of High-Performance RISC Cores with VHDL / T. Bautista, G. Marrero and P. Carballo [et al.] -- OOVHDL: Object Oriented VHDL / B. Djafri and J. Benzakki -- SUAVE: Painless Extension for an Object-Oriented VHDL / P. Ashenden, P. Wilsey and D. Martin -- A Requirements Analysis of Proposed Object Oriented VHDL Abstractions / M. Mills --
• Processes with "Incomplete" Sensitivity Lists and their Synthesis Aspects / E. Molenkamp and G. Mekenkamp -- A Symbol Based Algorithm for Hardware Implementation of Cyclic Redundancy Check (CRC) / R. Nair, G. Ryan and F. Farzaneh -- Fast Prototyping of an ASIC for ATM Applications using a Synthesizable VHDL Flexible Library / S. Claretto, E. Filippi and A. Montanaro [et al.] -- Extending VHDL to the Systems Level / P. Alexander and P. Baraona -- Semantics based Co-Specifications to Design DSP Systems / X. Warzee and P. Kajfasz -- Proposing Graphic Extensions to VHDL / T. Hadlich -- RTL Based Scan BIST / S. Roy -- Redesign of a Generic VHDL Model Template for SRAMs / C. McCloskey, R. Reese and V. Sanders -- Supporting Hardware Trade Analysis and Cost Estimation using Design Complexity / P. Salchak and P. Chawla -- SCUBA: An HDL Data-Path/Memory Module Generator for FPGAs / S. Mohanty, K. Maheswaran and S. Haruyama [et al.] --
• Reducing FPGA Design Modification Time / M. Lehky and S. Bilik -- Use of VHDL within a System Level Design Flow / T. Hadlich -- Extraction of Token Based VHDL Models from Old ASIC Net Lists / D. Soderberg -- VHDL Design Environment for Legacy Electronics (VDELE) / L. Concha, J. Houston and R. Bohannan -- Reuse through Genericity in SUAVE / P. Ashenden, P. Wilsey and D. Martin -- VHDL Modeling and Tutoring Efforts by Mississippi State University / R. Reese and D. Brown -- VHDL Models Supporting a System-Level Design Process: A RASSP Approach / J. DeBardelaben, V. Madisetti and A. Gadient -- Improvements to ADEPT - A VHDL Based Integrated Design Environment for Performance and Dependability Analysis / R. Klenke, J. Aylor and B. Johnson [et al.] -- Hardware/Software Codesign of a Scalable Embedded Radar Signal Processor / C. Buenzli, L. Owen and F. Rose -- VHDL-Based Performance Modeling: An Application of the PMW Tool Suite to an Image Classification System / J. Ammon and C. Hein --
• Building a Test Environment Component in VHDL for an Infrared Link Access Protocol (IrLAP) Compliant ASIC Interface / M. McKinney -- Component Modeling for Reliability Analysis by Simulation / B. Alizadeh and Z. Navabi -- A Model-Year Architecture Approach to Hardware Reuse in Digital Signal Processor System Design / J. Wedgwood and G. Buchanan -- Hardware/Software Co-Design in the Rapid Prototyping of Application-Specific Signal Processors Methodology / W. Schaming -- IEEE VHDL 1076.1: Mixed-Signal Behavioral Modeling and Verification in View of Automotive Applications / J. Papanuskas -- A Hybrid Event-Simulation/Cycle-Simulation Environment for VHDL-Based Designs / M. Cogswell and D. Wood -- On Comparing Different Modeling Styles / W. Ecker, J. Bottger and C. Ruschmeyer -- A New Methodology and Generic Model Library for the Rapid Prototyping of Real-Time Image Processing Systems / D. Gibson, M. Teal and D. Ait-Boudaoud [et al.].

ISBN

• 0818681802
• 0818681810 (case)
• 0818681829 (microfiche)

LCCN

97074351

OCLC

ocm38240805

Owning Institutions

Columbia University Libraries