Research Catalog

Title

IDDQ testing : digest of papers : IEEE International Workshop on IDDQ Testing, November 5-6, 1997, Washington, D.C. / edited by Anura P. Jayasumana ; sponsored by IEEE Computer Society Technical Committee on Test Technology.

Author

IEEE International Workshop on IDDQ Testing (3rd : 1997 : Washington, D.C.)

Publication

Los Alamitos, Calif. : IEEE Computer Society Press, [1997], ©1997.

Items in the Library & Off-site

Details

Additional Authors

• Jayasumana, Anura P.
• IEEE Computer Society. Test Technology Technical Committee.

Description

ix, 119 pages : illustrations; 28 cm

Subject

• Iddq testing > Congresses
• Metal oxide semiconductors, Complementary > Testing > Congresses

Note

• "IEEE Computer Society Press order number PR08123"--T.p. verso.
• "IEEE order plan catalog number 97TB100169"--T.p. verso.

Bibliography (note)

• Includes bibliographic references and author index.

Contents

• Keynote Speech: The Challenges of IDDQ Testing of Deep Sub-Micron ICs / Ron Walther -- Iddq Test Pattern Generation for Scan Chain Latches and Flip-Flops / S. R. Makar and E. J. McCluskey -- Random Testing with Partial Circuit Duplication and Monitoring I[subscript DDQ] / H. Yokoyama, X. Wen and H. Tamamoto -- Sequential Circuit Test Generation for IDDQ Testing of Bridging Faults / Y. Higami, T. Maeda and K. Kinoshita -- I[subscript DDQ] Testable Dynamic PLAs / M. Sachdev and H. Kerkhoff -- I[subscript CCQ]: A Test Method for Analogue VLSI Based on Current Monitoring / J. P. M. van Lammeren -- A Design for Test Proposal for Improving Dynamic Current Testing Reliability on Regenerative Sense Amplifiers / J. Arguelles and S. Bracho -- Current-Mode Techniques for Self-Testing Analogue Circuits / I. Baturone, S. Sanchez-Solano and A. M. Richardson [et al.] -- A Comprehensive Wafer Oriented Test Evaluation (WOTE) Scheme for the IDDQ Testing of Deep Sub-Micron Technologies / A. D. Singh --
• I[subscript DDQ] Testing of a 180MHz HP PA-RISC Microprocessor with Redundancy Programmed Caches / T. Meneghini and D. Josephson -- I[subscript DDQ] Testing for Submicron CMOS IC Technology Qualification / J. M. Soden -- STBM: A Framework for Stimulating and Selecting I[subscript DDQ] Measurement Points for Leakage Faults / S. Chakravarty, S. T. Zachariah and P. J. Thadikaran -- A Hybrid (Logic+I[subscript DDQ]) Testing Strategy Using an Iterative Bridging Fault Filtering Scheme / T. Chen and I. N. Hajj -- Estimation of Partition Size for I[subscript DDQ] Testing using Built-In Current Sensing / S. M. Menon and M. Palmgren -- An Approach for Detecting Bridging Fault-Induced Delay Faults in Static CMOS Circuits using Dynamic Power Supply Current Monitoring / A. Walker and P. K. Lala -- A Simulation-Based Method for Estimating Defect-Free IDDQ / P. C. Maxwell and J. R. Rearick -- On-Line CMOS BICS: An Experimental Study / Y. Maidon, Y. Deval and J. Tomas [et al.] --
• A High-Speed Low-Voltage Built-In Current Sensor / T.-C. Huang, M.-C. Huang and K.-J. Lee -- Tutorial: Reliability, Test, and I[subscript DDQ] Measurements / C. F. Hawkins, A. Keshavarzi and J. M. Soden -- Detecting Bridging Faults in Dynamic CMOS Circuits / J. T.-Y. Chang and E. J. McCluskey -- A Current Sensing Circuit for Feedback Bridging Faults / M. Hashizume, M. Ichimiya and T. Tamesada -- Simulation of Logic/IDDQ Tests for Resistive Shorts in Logic Circuits by Using Simplicial Approximation / H.-J. Lin and L. Milor.

ISBN

• 0818681233 (softbound)
• 081868125X (microfiche)

LCCN

97072789

OCLC

• 254697288
• ocn254697288

Owning Institutions

Columbia University Libraries