Research Catalog

Title

International Verilog HDL Conference and VHDL International Users Forum : March 16-19, 1998, Santa Clara, CA / sponsored by Open Verilog International VHDL International ; in cooperation with IEEE Computer Society Electronics Industries Association Japan.

Author

International Verilog HDL Conference and VHDL International Users Forum (1st : 1998 : Santa Clara, Calif.)

Publication

Los Alamitos, CA : IEEE Conmputer Society, [1998], ©1998.

Items in the Library & Off-site

Holdings

Details

Description

xiii, 202 pages : illustrations; 28 cm

Subjects

• Electronic circuit design > Data processing > Congresses
• Verilog (Computer hardware description language) > Congresses
• VHDL (Computer hardware description language) > Congresses

Note

• IEEE Computer Society Order Number PR08415.
• IEEE Order Plan Catalog Number 98TB100230.

Bibliography (note)

• Includes bibliographical references and index.

Contents

• Integrating of Verilog-HDL and VHDL Languages in the SMASH Mixed-signal Multi-level Simulator / P. Sauge and G. Thuau -- A Case Study of Compaq's Simulation Environment Migration to Windows NT / W. R. Stresau -- Incremental Compilation in the VCS Environment / V. K. Sundar, A. V. Naik and D. R. Chowdhury -- Transitioning to the New PLI Standard / S. Sutherland -- Implementing C Designs in Hardware: A Full-Featured ANSI C to RTL Verilog Compiler in Action / D. Soderman and Y. Panchul -- A Procedural Language Interface for VHDL and Its Typical Applications / F. Martinolle and A. Sherer -- VHDL 200x - Requirements from Testbench-View / M. Bauer, W. Ecker and M. Heuchling -- Considerations on System-Level Behavioural and Structural Modeling Extensions to VHDL / P. J. Ashenden and P. A. Wilsey -- Practical FSM Analysis for Verilog / T.-H. Wang and T. Edsall -- Guidelines for Safe Simulation and Synthesis of Implicit Style Verilog / M. G. Arnold, N. J. Sample and J. D. Shuler --
• Verilog Nonblocking Assignments Demystified / C. E. Cummings -- Process-Level Modeling with VHDL / J. Armstrong -- Tools for Rapid Construction of VHDL Performance Models for DSP Systems / F. G. Gray, G. A. Frank and B. Clark [et al.] -- Modeling Communication with Objective VHDL / W. Putzke-Roming, M. Radetzki and W. Nebel -- Application of VHDL to Software Radio Technology / J. McCloskey -- Verilog Plus C Language Modeling with PLI 2.0: The Next Generation Simulation Language / S. Meyer -- EP3: An Extensible Perl PreProcessor / G. Spivey -- A Mixed-Language Simulator for Concurrent Engineering / D. A. Burgoon -- A Strategy for C-Based Verification / P. Herman -- Reuse of Models and Testbenches at Different Levels of Abstraction / G. A. Frank, F. G. Gray and S. Gopalakrishnan [et al.] -- ModelMaker: A Tool for Rapid Modeling from Device Descriptions / W. R. Cyre and A. Gunawan --
• Improving VHDL Soft-Cores Reuse with Software-like Reviews and Audits Procedures / S. Olcoz, A. Castellvi and M. Garcia -- Overcoming the Limitations of Self-Checking Stimulus through the Use of an ASIC Mirror / R. D. Benson -- A Pseudorandom Test Environment / R. F. Beckwith, B. Wood and B. Rioux [et al.] -- Networked Object Oriented Verification with C++ and Verilog / G. Dearth, S. Meeth and P. Whittemore -- A Loosely Coupled C/Verilog Environment for System Level Verification / A. S. Meyer -- A Functional Test Planning System for Validation of DSP Circuits Modeled in VHDL / M.-W. Lin, J. R. Armstrong and G. A. Frank [et al.] -- Scan Parallel Loading in VHDL / J. P. Vo -- STG Timing Extensions and Simulation / M. V. Goncharov, A. B. Smirnov and I. V. Klotchkov [et al.] -- SAVANT/TyVIS/WARPED: Components for the Analysis and Simulation of VHDL / P. A. Wilsey, D. E. Martin and K. Subramani.

ISBN

0818684151

OCLC

ocm39096811

Owning Institutions

Columbia University Libraries