Research Catalog
A VHDL primer
- Title
- A VHDL primer / J. Bhasker.
- Author
- Bhasker, Jayaram.
- Publication
- Upper Saddle River, N.J. : Prentice Hall PTR, [1999], ©1999.
Items in the Library & Off-site
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1 Item
| Status | Format | Access | Call Number | Item Location |
|---|---|---|---|---|
| Text | Request in advance | TK7885.7 .B53 1999g | Off-site |
Holdings
Details
- Description
- xx, 373 pages : illustrations; 25 cm
- Summary
- This introduction to VHDL focuses on the features you need to get results - with extensive practical examples so you can start writing VHDL models immediately. Written by J. Bhasker, one of the world's leading VHDL course developers, this best-selling guide has been completely updated to reflect the popular IEEE STDL̲OGIC1̲164 package.
- Subjects
- Bibliography (note)
- Includes bibliographical references (p. [363]-365) and index.
- Contents
- Ch. 1. Introduction -- Ch. 2. A Tutorial -- Ch. 3. Basic Language Elements -- Ch. 4. Behavioral Modeling -- Ch. 5. Dataflow Modeling -- Ch. 6. Structural Modeling -- Ch. 7. Generics and Configurations -- Ch. 8. Subprograms and Overloading -- Ch. 9. Packages and Libraries -- Ch. 10. Advanced Features -- Ch. 11. Model Simulation -- Ch. 12. Hardware Modeling Examples -- App. A. Predefined Environment -- App. B. Syntax Reference -- App. C. A Package Example -- App. D. Summary of Changes -- App. E. The STDL̲OGIC1̲164 Package -- App. F. An Utility Package.
- ISBN
- 0130965758
- OCLC
- ocm40003891
- Owning Institutions
- Columbia University Libraries