Research Catalog

Formal verification of circuits

Title
Formal verification of circuits / Rolf Drechsler.
Author
Drechsler, Rolf.
Publication
Boston : Kluwer Academic Publishers, [2000], ©2000.

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TextRequest in advance TK7867 .D7 2000Off-site

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Details

Description
x, 179 pages : illustrations; 24 cm
Subject
  • Electronic circuits > Testing
  • Decision trees
Bibliography (note)
  • Includes bibliographical references and index.
Contents
1. Introduction -- 2. Notations and Definitions -- 3. Decision Diagrams. 3.1. Bit-Level Decision Diagrams. 3.2. Word-Level Decision Diagrams -- 4. Theoretical Aspects of WLDDs. 4.1. Basic Properties. 4.2. Why to Use Edge Values. 4.3. Why to Use different Decomposition Types. 4.4. Why to use "many" DTLs. 4.5. Representation Size of Arithmetic Functions -- 5. Implementation of WLDDs. 5.1. Synthesis Operations: Classical Approach. 5.2. WLDDs Representing Boolean Functions. 5.3. Compilation -- 6. Minimization of DDS. 6.1. Reordering. 6.2. Dynamic Minimization of WLDDs. 6.3. Grouping. 6.4. Lower Bound Sifting. 6.5. History-based Dynamic Minimization. 6.6. Exact BDD Minimization -- 7. Arithmetic Circuits. 7.1. Addition. 7.2. Multiplication. 7.3. Division. 7.4. Floating Point Circuits -- 8. Verification of HDLS. 8.1. Modulo Operation. 8.2. Division. 8.3. Datapath Operations. 8.4. A Case Study -- 9. Conclusions.
ISBN
079237858X (alk. paper)
LCCN
00034888
OCLC
  • 44026134
  • ocm44026134
  • SCSB-3943266
Owning Institutions
Columbia University Libraries