Research Catalog
Systematic design for optimisation of pipelined ADCs
- Title
- Systematic design for optimisation of pipelined ADCs / by João Goes, João C. Vital, and José Franca.
- Author
- Goes, João.
- Publication
- Boston : Kluwer Academic Publishers, [2001], ©2001.
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1 Item
| Status | Format | Access | Call Number | Item Location |
|---|---|---|---|---|
| Text | Request in advance | TK7887.6 .C64 2001 | Off-site |
Holdings
Details
- Additional Authors
- Description
- xv, 160 pages : illustrations; 25 cm.
- Series Statement
- The Kluwer international series in engineering and computer science ; SECS 607. Analog circuits and signal processing
- Uniform Title
- Kluwer international series in engineering and computer science ; SECS 607.
- Kluwer international series in engineering and computer science. Analog circuits and signal processing.
- Subjects
- Bibliography (note)
- Includes bibliographical references.
- Contents
- Ch. 1. Introduction -- Ch. 2. General Design Considerations in Pipelined A/D Converters. Performance Parameters in Nyquist A/D Converters. Main Non-Idealities in Pipelined A/D Converters. Overview and Comparison of Published Works in Pipelined A/D Converters -- Ch. 3. Analogue Code-by-Code Self-Calibration Technique. System Architecture. The Self-Calibration Technique. Integrated MDAC Prototype and Measured Results. Behavioural System Simulations of a High-Resolution Pipelined ADC -- Ch. 4. Systematic Design Methodology for Optimisation of High-Speed Self-Calibrated Pipelined ADCs. Architecture Description. Design Considerations. Power and Area Estimation. Optimisation. Design Example -- Ch. 5. Design of a 14-Bit 5 Ms/s CMOS Pipelined A/D Converter. Specifications, Architecture Definition and Background Self-Calibration of the Overall Conversion System. Design of the Basic Building Blocks. Design of the Overall System and Functional Simulations --
- Ch. 6. Integrated Prototypes of Pipelined ADCs and Measured Results. Integrated Prototype of an 8-Bit 2Ms/s Pipelined ADC with Minimum Bit-Stage Architecture. Integrated Prototype of a 14-Bit 5Ms/s Background Self-Calibrated Pipelined ADC with a Power/Area Optimised Architecture -- Ch. 7. Conclusions.
- ISBN
- 0792372913 (alk. paper)
- LCCN
- 00140204
- OCLC
- ocm45749838
- SCSB-4112901
- Owning Institutions
- Columbia University Libraries