Research Catalog

Title

Code optimization techniques for embedded processors : methods, algorithms, and tools / by Rainer Leupers.

Author

Leupers, Rainer.

Publication

Boston : Kluwer Academic Publishers, [2000], ©2000.

Items in the Library & Off-site

Holdings

Details

Description

viii, 216 pages : illustrations; 25 cm

Summary

• "Code Optimization Techniques for Embedded Processors discusses the state-of-the-art in the area of compilers for embedded processors. It presents a collection of new code optimization techniques, dedicated to DSP and multimedia processors. These include: compiler support for DSP address generation units, efficient mapping of data flow graphs to irregular architectures, exploitation of SIMD and conditional instructions, as well as function inlining under code size constraints.
• Comprehensive experimental evaluations are given for real-life processors, that indicate the code quality improvements which can be achieved as compared to earlier techniques. In addition, C compiler frontend issues are discussed from a practical viewpoint." "Code Optimization Techniques for Embedded Processors is intended for researchers and engineers active in software development for embedded systems, and for compiler developers in academia and industry."--BOOK JACKET.

Subject

• Embedded computer systems > Programming

Bibliography (note)

• Includes bibliographical references (p. 197-212) and index.

Contents

1. Introduction -- 2. Memory Adress Computation for DSPS -- 3. Register Allocation for DSP Data Paths -- 4. Instruction Scheduling for Clustered VLIW Processors -- 5. Code Selection for Multimedia Processors -- 6. Performance Optimization with Conditional Instructions -- 7. Function Inlining under Code Size Constraints -- 8. Frontend Issues - The Lance System -- 9. Conclusions -- App. A. Experimental Result Tables -- App. B. Example for the LANCE V2.0 IR.

ISBN

0792379896 (alk. paper)

LCCN

00046970

OCLC

• ocm45002213
• SCSB-4122480

Owning Institutions

Columbia University Libraries