Research Catalog
IEEE European Test Workshop : proceedings : 29 May-1 June, 2001, Stockholm, Sweden
- Title
- IEEE European Test Workshop : proceedings : 29 May-1 June, 2001, Stockholm, Sweden / sponsored by, IEEE Computer Society Test Technology Technical Council (TTTC), Linköping University (LiU) ; in cooperation with, Ericsson [and others].
- Author
- IEEE European Test Workshop (2001 : Stockholm, Sweden)
- Publication
- Los Alamitos, California : IEEE Computer Society Press, [2001], ©2001.
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Status | Format | Access | Call Number | Item Location |
---|---|---|---|---|
Text | Request in advance | TK7874 .E7951 2001g | Off-site |
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Details
- Additional Authors
- Description
- xxi, 147 pages : illustrations; 28 cm
- Alternative Title
- ETW 2001
- Subject
- Note
- "IEEE Computer Society Order Number PR01016"--verso of T.p.
- "ETW 2001"--cover.
- Bibliography (note)
- Includes bibliographic references and author index.
- Contents
- Analyzing Bridging Faults Impact on EEPROM Cell Array / J. Portal and A. Perez -- Internal Feedback Bridging Faults in Combinational CMOS Circuits: Analysis and Testing / Y. Miura and S. Seno -- System-Level DfT for Consumer Products / D. van Geest and F. de Jong -- A Fault Model for Function and Delay Testing / J. Yi and J. Hayes -- Reducing the Susceptibility of Design-for-Delay-Testability Structures to Process- and Application-Induced Variations / H. Vermaak and H. Kerkhoff -- Demodulation Based Testing of Off-Chip Driver Performance / W. Daehn -- Automated Regression Testing of CTI-Systems / O. Niese, T. Margaria and A. Hagerer / [et al.] -- Reducing Analogue Fault-Simulation Time by Using High-Level Modelling in Dotss for an Industrial Design / L. Fang, G. Gronthoud and H. Kerkhoff -- On-Chip Signal Level Evaluation for Mixed-Signal ICs Using Digital Window Comparators / D. De Venuto, M. Ohletz and B. Ricco --
- The Use of Equivalent Fault Analysis to Improve Static D.C. Fault Diagnosis - A Potentiometric DAC Case Study / M. Worsman, M. Wong and Y. Lee -- A Packet Switching Communication-Based Test Access Mechanism for System Chips / M. Nahvi and A. Ivanov -- System Level Diagnosis - A Comparison of Two Alternative Approaches / M. Khalil, C. Robach and F. Novak / [et al.] -- RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage / M. Santos, F. Goncalves and I. Teixeira / [et al.] -- An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures / V. Zivkovic, R. Tangelder and H. Kerkhoff -- On Hardware Generation of Random Single Input Change Test Sequences / R. David, P. Girard and C. Landrault / [et al.] -- Reusing Scan Chains for Test Pattern Decompression / R. Dorsch and H.-J. Wunderlich -- A VHDL-Based Virtual Test Concept for Pre-silicon Test-Program Debug / M. Rona and G. Krampl --
- Using At-Speed BIST to Test LVDS Serializer/Deserializer Function / M. Eckersand, F. Franzon and K. Filliter.
- ISBN
- 0769510167
- 0769510175 (case)
- 0769510183 (microfiche)
- OCLC
- ocm47921776
- SCSB-4176074
- Owning Institutions
- Columbia University Libraries