Research Catalog

Title

FPGA : ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA : February 23-25, 2003 / sponsored by ACM SIGDA ; with support from Altera, Xilinx, Actel.

Author

ACM International Symposium on Field-Programmable Gate Arrays (11th : 2003 : Monterey, Calif.)

Publication

New York, N.Y. : ACM Press, c2003.

Items in the Library & Off-site

Details

Additional Authors

• Trimberger, Stephen, 1955-
• Tessier, Russell G. (Russell George)
• ACM Special Interest Group on Design Automation
• Altera Corporation
• Xilinx (Firm)
• Actel Corporation

Description

vii, 249 p. : ill.; 28 cm.

Alternative Title

• ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays
• FPGA 2003
• International Symposium on Field Programmable Gate Arrays
• Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays.

Subject

• Gate array circuits > Congresses
• Field programmable gate arrays > Congresses
• Programmable array logic > Congresses

Note

• ACM order number 480030.
• "Steve Trimberger, general chair, Russ Tessier, program chair"--P. iii.

Additional Formats (note)

• Also available on the World Wide Web via ACM Digital Library with title: Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays.

Contents

Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores / N. Kafafi, K. Bozman and S. J. E. Wilton -- The Stratix Routing and Logic Architecture / D. Lewis, V. Betz, P. Laventis, S. Marquardt, J. Rose, D. Jefferson, A. Lee, C. Lane, C. McClintock, B. Pedersen, G. Powell, S. Reddy, C. Wysocki and R. Cliff -- A Pipelined Configurable Gate Array for Embedded Processors / A. Lodi, M. Toma, F. Campi, A. Cappelli, R. Guerrieri and R. Canegallo -- Hardware-Assisted Simulated Annealing with Application for Fast FPGA Placement / M. G. Wrighton and A. M. DeHon -- Parallel Placement for Field-Programmable Gate Arrays / P. K. Chan and M. D. F. Schlag -- I/O Placement for FPGAs with Multiple I/O Standards / W.-K. Mak -- Wire Type Assignment for FPGA Routing / S. Lee, H. Xiang, D. F. Wong and R. Y. Sun -- PipeRoute: A Pipelining-Aware Router for FPGAs / A. Sharma, C. Ebeling and S. Hauck -- Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes / R. Huang, J. Wawrzynek and A. DeHon -- Implementation of BEE: a Real-Time Large-scale Hardware Emulation Engine / C. Chang, B. Richards, R. W. Brodersen and K. Kuusilinna -- High-Level Modeling and FPGA Prototyping of Microprocessors / J. Ray and J. C. Hoe -- Reducing Pin and Area Overhead in Fault-Tolerant FPGA-based Designs / F. Lima, L. Carro and R. Reis -- Attack of the Killer Gate Arrays / Michael Butts -- Placement-Driven Technology Mapping for LUT-Based FPGAs / J. Y. Lin, A. Jagannathan and J. Cong -- Verifying the Correctness of FPGA Logic Synthesis Algorithms / B. Ratchev, M. Hutton, G. Baeckler and B. van Antwerpen -- Using Logic Duplication to Improve Performance in FPGAs / K. Schabas and S. D. Brown -- A Scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS Technology / J. R. Guo, C. You, K. Zhou, R. P. Kraft, J. F. McDonald and B. S. Goda -- Design of FPGA Interconnect for Multilevel Metalization / R. Rubin and A. DeHon -- Automatic Transistor and Physical Design of FPGA Tiles from an Architectural Specification / K. Padalia, R. Fung, M. Bourgeault, A. Egier and J. Rose -- Architecture Evaluation for Power-Efficient FPGAs / F. Li, D. Chen, L. He and J. Cong -- Post-Placement C-slow Retiming for the Xilinx Virtex FPGA / N. Weaver, Y. Markovskiy, Y. Patel and J. Wawrzynek -- An FPGA Architecture with Enhanced Datapath Functionality / K. Leijten-Nowak and J. L. van Meerbergen -- A Fully Pipelined Memoryless 17.8 Gbps AES-128 Encryptor / K. U. Jarvinen, M. T. Tommiska and J. O. Skytta -- A Methodology to Implement Block Ciphers in Reconfigurable Hardware and its Application to Fast and Compact AES RIJNDAEL / F.-X. Standaert, G. Rouvroy, J.-J. Quisquater and J.-D. Legat -- Energy-Efficient Signal Processing Using FPGAs / S. Choi, R. Scrofano, V. K. Prasanna and J.-W. Jang -- Poster Abstracts.

ISBN

158113651X

OCLC

• ocm52644074
• SCSB-4814070

Owning Institutions

Columbia University Libraries