Research Catalog
Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA
- Title
- Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA / Alexander Starikov, chair/editor ; sponsored ... by SPIE--the International Society for Optical Engineering.
- Publication
- Bellingham, Wash. : SPIE, c2003.
Items in the Library & Off-site
Filter by
1 Item
| Status | Format | Access | Call Number | Item Location |
|---|---|---|---|---|
| Text | Use in library | TK7874 .D377 2003g | Off-site |
Details
- Additional Authors
- Description
- viii, 418 p. : ill.; 28 cm.
- Series Statement
- SPIE proceedings series, 0277-786X ; v. 5042
- Uniform Title
- Design, process integration, and characterization for microelectronics.
- Proceedings of SPIE--the International Society for Optical Engineering ; v. 5042.
- Subjects
- Semiconductor wafers > Defects > Analysis > Congresses
- Integrated circuits > Defects > Analysis > Congresses
- Integrated circuits > Design and construction > Congresses
- Microelectronics industry > Quality control > Congresses
- Semiconductors > Design and construction > Congresses
- Quality control > Congresses
- Note
- 2002 conference proceedings titled: Design, process integration, and characterization for microelectronics.
- Bibliography (note)
- Includes bibliographical references and index.
- Contents
- Layout optimization at the pinnacle of optical lithography / L. W. Liebmann, G. A. Northrop, J. Culp, L. Sigal, A. Barish and C. A. Fonseca -- Dense-only phase-shift template lithography / M. Fritze, B. Tyrrell, R. D. Mallen, B. Wheeler, P. D. Rhyins and P. M. Martin -- Assessing technology options for 65-nm logic circuits / D. Pramanik, M. L. Cote, K. Boaudette and V. Axelrad -- Generalization of the photo process window and its application to OPC test pattern design / H. Eisenmann, K. Peter and A. J. Strojwas -- Physical and timing verification of subwavelength-scale designs: I. lithography impact on MOSFETs / R. C. Pack, V. Axelrad, A. Shibkov, V. V. Boksha, J. A. Huckabay, R. Salik, W. Staud, R. Wang and W. D. Grobman -- Technology CAD for integrated circuit fabrication technology development and technology transfer / S. Saha -- Performance-Impact limited-area fill synthesis / Y. Chen, P. Gupta and A. B. Kahng -- Simulation-based data processing using repeated pattern identification / Y. Zhang -- Model-assisted placement of subresolution assist features: experimental results / T. E. Brist and J. A. Torres -- OPC on real-world circuitry / S. C. O'Brien, T. Aton, M. E. Mason, C. Vickery and J. N. Randall -- OPC methods to improve image slope and process window / N. B. Cobb and Y. Granik -- Lithography-driven layout of logic cells for 65-nm node / D. Pramanik and M. L. Cote -- Improved manufacturability by OPC based on defocus data / J. Thiele, I. Anke, H. Haffner and A. Semmler -- LithoScope: an advanced physical modeling system for mask data verification / Q.-D. Qian -- Effective multicutline QUASAR illumination optimization for SRAM and logic / T. E. Brist and G. E. Bailey -- Investigation of product design weaknesses using model-based OPC sensitivity analysis / S. V. Postnikov, K. Lucas, C. M. Garza, K. Wimmer, P. LaCour and J. C. Word -- Device characteristics of sub-20-nm silicon nanotransistors / S. Saha -- NBTI improvement for pMOS by Cl-contained 1[superscript st] oxidation in 20A/65A dual-nitrided gate oxide of 0.13-[mu]m CMOS technology / C.-C. Hao, M.-H. Chi, C.-C. Chen, H.-J. Lin, Y.-F. Lin, C. H. Hsieh, C. H. Lee, K. H. Chang, H. T. Wu and C.-H. Shen -- Library-based process test vehicle design framework / K. Y.-Y. Doong, L.-J. Hung, S. Ho, S. C. Lin and K. L. Young -- Design-to-process integration: optimizing 130-nm X architecture manufacturing / R. Dean, V. K. Malhotra, N. King, M. Sanie, S. S. MacDonald, J. D. Jordan and S. Hirukawa -- Using the CODE technique to print complex two-dimensional structures in a 90-nm ground rule process / S. Manakli, Y. Trouiller, O. Toublan, P. Schiavone, Y. F. Rody and P. J. Goirand -- New stream formal: progress report on containing data size explosion / P. LaCour, A. J. Reich, K. H. Nakagawa, S. F. Schulze and L. Grodd -- Optimization of the data preparation for variable-shaped beam mask writing machines / S. F. Schulze and P. LaCour -- Compression algorithms for dummy-fill VLSI layout data / R. B. Ellis, A. B. Kahng and Y. Zheng -- Characterization and modeling of intradie variation and its applications to design for manufacturability / S. Saxena, C. Guardiani, M. Quarantelli, N. Dragone, S. Minehane, P. McNamara and J. A. Babcock -- Applications of image diagnostics to metrology quality assurance and process control / J. A. Allgair, V. V. Boksha, B. D. Bunday, A. C. Diebold, D. C. Cole, M. P. Davidson, J. D. Hutcheson, A. W. Gurnell, D. C. Joy, J. M. McIntosh, S. G. Muckenhirn, J. C. Pellegrini, R. D. Larrabee, J. E. Potzick, A. E. Vladar, N. P. Smith, A. Starikov, N. T. Sullivan and O. C. Wells -- Creation and verification of phase-compliant SoC hard IP for the fabless COT designers / V. K. Malhotra, N. King, R. Leung, Z. Zia and S. Jeawoody -- Statistical data assessment for optimization of the data preparation and manufacturing / S. F. Schulze and P. LaCour -- Lithographic tradeoffs between different assist feature OPC design strategies / J. C. Word and S. Zhu -- Resolution enhancement technology requirements for 65-nm node / A. Kroyan and H. Liu -- PsmLint: bringing AltPSM benefits to the IC design stage / P. Ghosh, C. Kang, M. Sanie and J. A. Huckabay -- Optimizing manufacturability for the 65-nm process node / D. Pramanik and M. L. Cote -- Optimized cobalt silicide formation through etch process improvements / D. S. Tucker, R. Yang and H. Maines -- Modification of existing chip layout for yield and reliability improvement by computer-aided design tools / M.-J. Li, S. Maturi and P. Dixit -- Precision control of poly-gate CD by local OPC for elimination of microloading effect on 0.13-[mu]m CMOS technology / T.-K. Lee, Y.-C. Wang, M.-H. Chi, C. Y. Lu, C. H. Hsieh, R. G. Liu, H. J. Liao, S. S. Yang and C.-H. Chang -- Process, design, and optical proximity correction requirements for the 65-nm device generation / K. Lucas, P. Montgomery, L. C. Litt, W. Conley, S. V. Postnikov, W. Wu, C.-M. Yuan, M. Olivares, K. Strozewski, R. L. Carter, J. Vasek, D. Smith, E. L. Fanucchi, V. Wiaux, G. Vandenberghe, O. Toublan, A. Verhappen, J. P. Kuijten, J. van Wingerden, B. S. Kasprowicz, J. W. Tracy, C. J. Progler, E. Shiro, I. Topouzov, K. Wimmer and B. J. Roman -- Optical rule checking for proximity-corrected mask shapes / M. Mukherjee, Z. Baum, J. Nickel and T. G. Dunham -- Failure prediction across process window for robust OPC / S. D. Shang, Y. Granik, N. B. Cobb, W. Maurer, Y. Cui, L. W. Liebmann, J. M. Oberschmidt, R. N. Singh, J. Watson and B. R. Vampatella -- A methodology to calculate line-end correction feature performance as a function of reticle cost / L. S. Melvin III, J. P. Shiely, M. L. Rieger and B. Painter -- Trends in systematic nonparticle yield loss mechanisms and the implication for IC design / C. N. Berglund -- Impact of inter-mask CD error on OPC accuracy in resolution of 90 nm and below / K. Ozawa, S. Sato and H. Ohnuma.
- ISBN
- 0819448478
- OCLC
- ocm52734795
- SCSB-4823427
- Owning Institutions
- Columbia University Libraries