Research Catalog

Title

ISLPED'05 : proceedings of the 2005 International Symposium on Low Power Electronics and Design, Hotel Marriott del Mar, San Diego, California, USA, August 8-10, 2005 / sponsored by ACM SIGDA and IEEE Circuits and Systems Society ; with technical support from the IEEE Solid-State Circuits Society and the IEEE Electron Devices Society.

Author

International Symposium on Low Power Electronics and Design (10th : 2005 : San Diego, Calif.)

Publication

New York, N.Y. : Association for Computing Machinery, [2005], ©2005.

Items in the Library & Off-site

Holdings

Details

Additional Authors

• ACM Special Interest Group on Design Automation.
• IEEE Circuits and Systems Society.
• IEEE Solid-State Circuits Society.
• IEEE Electron Devices Society.
• Association for Computing Machinery.

Description

xiv, 402 pages : illustrations; 28 cm

Alternative Title

• Proceedings of the 2005 International Symposium on Low Power Electronics and Design
• 2005 International Symposium on Low Power Electronics and Design
• Low power electronics and design
• Low Power Electronics and Design, 2005, ISLPED '05, Proceedings of the 2005 International Symposium on.

Subject

• Power electronics > Congresses

Note

• "ACM Order Number 477054"--P. ii.
• "IEEE Catalog Number: 05TH8842"--P. ii.

Bibliography (note)

• Includes bibliographical references and author index.

Additional Formats (note)

• Also available on the World Wide Web via ACM Digital Library.
• Also issued online with additional title: Low Power Electronics and Design, 2005, ISLPED '05, Proceedings of the 2005 International Symposium on.

Contents

• Technology and design challenges for mobile communication and computing products / D. Buss -- FinFET-based SRAM design / Z. Guo, S. Balasubramnian, R. Zlatanovici, T.-J. King and B. Nikolic -- Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits / S. Mukhopadhyay, K. Kim, C.-T. Chuang and K. Roy -- Effectiveness of low power dual-V[subscript t] designs in nano-scale technologies under process parameter variations / A. Agarwal, K. Kang, S. K. Bhunia, J. D. Gallagher and K. Roy -- Analysis and mitigation of variability in subthreshold design / B. Zhai, S. Hanson, D. Blaauw and D. Sylvester -- Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage / A. Keshavarzi, G. Schrom, S. Tang, S. Ma, K. Bowman, S. Tyagi, K. Zhang, T. Linton, N. Hakim, S. Duvall, J. Brews and V. De -- Instruction packing : reducing power and delay of the dynamic scheduling logic / J. J. Sharkey, D. V. Ponomarev, K. Ghose and O. Ergin -- Energy-efficient and high-performance instruction fetch using a block-aware ISA / A. Zmily and C. Kozyrakis -- Energy-aware fetch mechanism : trace cache and BTB customization / D. Chaver, M. A. Rojas, L. Pinuel, M. Prieto, F. Tirado and M. C. Huang -- Understanding the energy efficiency of SMT and CMP with multiclustering / J. Cong, A. Jagannathan, G. Rienman and Y. Tamir -- A simple mechanism to adapt leakage-control policies to temperature / S. Kaxiras, P. Xekalakis and G. Keramidas -- A 120nm low power asynchronous ADC / E. Allier, J. Goulier, G. Sicard, A. Dezzani, E. Andre and M. Renaudin -- A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13 [mu]m CMOS / X. Chen and Q. Huang -- A low power current steering digital to analog converter in 0.18 micron CMOS / D. Mercer -- Systematic power reduction and performance analysis of mismatch limited ADC designs / P. C. S. Scholtens, D. Smola and M. Vertregt -- A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications / L. A. Milner and G. a. Rincon-Mora -- A GHz-class charge recovery logic / V. S. Sathe, M. C. Papaefthymiou and C. H. Ziesler -- Low-power fanout optimization using multiple threhold voltage inverters / B. Amelifard, F. Fallah and M. Pedram -- A low-power bus design using joint repeater insertion and coding / S. R. Sridhara and N. R. Shanbhag -- An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS / S. K. Hsu, A. Agarwal, K. Roy, R. K. Krishnamurthy and S. Borkar -- A low-power, multichannel gated oscillator-based CDR for short-haul applications / A. Tajalli, P. Muller, M. Atarodi and Y. Leblebici -- An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs / K. Gulati, N. Jayakumar and S. P. Khatri -- Cascaded carry-select adder (C[superscript 2]SA) : a new structure for low-power CSA design / Y. Chen, H. Li, K. Roy and C.-K. Koh -- Region-level approximate computation rouse for power reduction in multimedia applications / X. Cheng and M. S. Hsiao -- Joint exploration of architectural and physical design spaces with thermal consideration / Y.-W. Wu, C.-L. Yang, P.-H. Yuh and Y.-W. Chang -- Coordinated, distributed, formal energy management of chip multiprocessors / P. Juang, Q. Wu, L.-S. Peh, M. Martonosi and D. W. Clark -- A probabilistic framework for power-optimal repeater insertion in global interconnects under paramoter variations / V. Wason and K. Banerjee -- Power-optimal repeater insertion considering V[subscript dd] and V[subscript th] as design freedoms / Y. C. Chang, K. H. Tam and L. He -- Probabilistic dual-V[subscript th] leakage optimization under variability / A. Davoodi and A. Srivastava -- Linear programming for sizing, V[subscript th] and V[subscript dd] assignment / D. G. Chinnery and K. Keutzer -- An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design / K.-H. Chen, K.-C. Chao, J.-S. Wang, Y.-S. Chu and J.-I. Guo -- Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications / M. Lanuzza, M. Margala and P. Corsonello -- Two efficient methods to reduce power and testing time / I.-S. Lee and T. Ambler -- Power and thermal effects of SRAM vs. latch-mux design styles and clock gating choices / Y. Li, M. Hempstead, P. Mauro, D. Brooks, Z. Hu and K. Skadron -- Platform trends for the digital home and enterprise / S. L. Smith -- Complexity reduction in an nRERL microprocessor / S. Kim and S.-I. Chae -- Driver pre-emphasis techniques for on-chip global buses / L. Zhang, J. Wilson, R. Bashirullah, L. Luo, J. Xu and P. Franzon -- Multi-story power delivery for supply noise reduction and low voltage operation / J. Gu and C. H. Kim -- Low power SRAM techniques for handheld products / R. Islam, A. Brand and D. Lippincott -- High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar / M. Sumita -- An evaluation of code and data optimizations in the context of disk power reduction / M. Kandemir, S. W. Son and G. Chen -- Optimizing sensor movement planning for energy efficiency / G. Wang, M. J. Irwin, P. Berman, H. Fu and T. La Porta -- Power prediction for Intel Xscale processors using performance monitoring unit events / G. Contreras and M. Martonosi -- Power reduction by varying sampling rate / W. R. Dieter, S. Datta and W. K. Kai -- Energy efficient strategies for deployment of a two-level wireless sensor network / A. Iranli, M. Maleki and M. Pedram -- Power grid voltage integrity verification / M. Nizam, F. N. Najm and A. Devgan -- The need for a full-chip and package thermal model for thermally optimized IC designs / W. Huang, E. Humenay, K. Shadron and M. R. Stan -- Peak temperature control and leakage reduction during binding in high level synthesis / R. Mukherjee, S. O. Memik and G. Memik -- LAP : a logic activity packing methodology for leakage power-tolerant FPGAs / H. Hassan, M. Anis and M. Elmasry -- Defocus-aware leakage estimation and control / A. B. Kahng, S. Muddu and P. Sharma -- Hierarchical power management with application to scheduling / P. Rong and M. Pedram -- Runtime identification of microprocessor energy saving opportunities / W. L. Bircher, M. Valluri, J. Law and L. K. John -- Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy / A. Ejlali, M. T. Schmitz, G. M. Al-Hashimi, S. G. Miremadi and P. Rosinger -- Bounds on power savings using runtime dynamic voltage scaling : an exact algorithm and a linear-time heuristic approximation / F. Xie, M. Martonosi and S. Malik -- Power-aware code scheduling for clusters of active disks / S. W. Son, G. Chen and M. Kandemir -- Wearable computing - a catalyst for business and entertainment / C. Narayanaswami -- Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes / D. Ma, J. M. Wang, M. N. Somasundaram and Z. Hu -- Accurate battery lifetime estimation using high-frequency power profile emulation / F. Simjee and P. H. Chou -- On-chip digital power supply control for system-on-chip applications / M. Miejer, J. Pineda de Gyvez and R. Otten -- Self-timed circuits for energy harvesting AC power supplies / J. Siebert, J. Collier and A. Amirtharajah -- A tunable bus encoder for off-chip data buses / D. C. Suresh, B. Agrawal and W. Najjar -- Fast configurable-cache tuning with a unified second-level cache / A. Gordon-Ross, F. Vahid and N. Dutt -- Dataflow analysis for energy-efficient scratch-pad memory management / G. Chen and M. Kandemir -- Energy reduction in multiprocessor systems using transactional memory / T. Moreshet, R. I. Bahar and M. Herlihy -- Inter-program optimizations for conserving disk energy / J. Hom and U. Kremer -- PARE : a power-aware hardware data prefetching engine / Y. Guo, M. Ben Naser and C. A. Moritz --
• Snug set-associative caches : reducing leakage power while improving performance / J.-J. Li and Y.-S. Hwang -- An energy efficient TLB design methodology / D. Fan, Z. Tang, H. Huang and G. R. Gao -- Synonymous address compaction for energy reduction in data TLB / C. S. Ballpuram, H.-H. S. Lee and M. Prvulovic -- A non-uniform cache architecture for low power system design / T. Ishihara and F. Fallah -- Replacing global wires with an on-chip network : a power analysis / S. Heo and K. Asanovic -- A low-power crossroad switch architecture and its core placement for network-on-chip / K.-C. Chang, J.-S. Shen and T.-F. Chen -- System level power and performance modeling of GALS point-to-point communication interfaces / K. Niyogi and D. Marculescu -- A technique for low energy mapping and routing in network-on-chip architectures / K. Srinivasan and K. S. Chatha -- Improving energy efficiency by making DRAM less randomly accessed / H. Huang, K. G. Shin, C. Lefurgy and T. Keller.

ISBN

1595931376

OCLC

• ocm61877455
• SCSB-5227762

Owning Institutions

Columbia University Libraries