Research Catalog

Title

FPGA 2005 : ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Resort, Monterey, California, USA : February 20-22, 2005 / sponsored by ACM SIGDA ; with support from Altera, Xilinx, Actel.

Author

ACM International Symposium on Field-Programmable Gate Arrays (13th : 2005 : Monterey, Calif.)

Publication

New York : Association for Computing Machinery, [2005], ©2005.

Items in the Library & Off-site

Holdings

Details

Additional Authors

• ACM Special Interest Group on Design Automation.
• Actel Corporation.
• Altera Corporation.
• Xilinx (Firm)

Description

vi, 282 pages : illustrations; 28 cm

Alternative Title

• ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays
• International Symposium on Field Programmable Gate Arrays
• FPGA '05
• Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays.

Subject

• Gate array circuits > Congresses
• Field programmable gate arrays > Congresses
• Programmable array logic > Congresses

Note

• "ACM order number 480050"--T.p. verso.

Bibliography (note)

• Includes bibliographical references and index.

Additional Formats (note)

• Also issued online with additional title: Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays.

Contents

Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits / A. Ye and J. Rose -- The Stratix II logic and routing architecture / D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cliff and J. Rose -- HARP : hard-wired routing pattern FPGAs / S. Sivaswamy, G. Wang, C. Ababei, K. Bazargan, R. Kastner and E. Bozorgzadeh -- Skew-programmable clock design for FPGA and skew-aware placement / C.-Y. Yeh and M. Marek-Sadowska -- The effect of post-layout pin permutation on timing / Y. Ding, P. Suaris and N. Chou -- Simultaneous timing-driven placement and duplication / G. Chen and J. Cong -- Sparse matrix-vector multiplication on FPGAs / L. Zhuo and V. K. Prasanna -- Floating-point sparse matrix-vector multiply for FPGAs / M. de Lorimier and A. DeHon -- 64-bit floating-point FPGA matrix multiplication / Y. Dou, S. Vassiliadis, G. K. Kuzmanov and G. N. Gaydadjiev -- Instruction set extension with shadow registers for configurable processors / J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman and Z. Zhang -- An FPGA-based VLIW processor with custom hardware execution / A. K. Jones, R. Hoare, D. Kusic, J. Fazekas and J. Foster -- Techniques for synthesizing binaries to an advanced register/memory structure / G. Stitt, Z. Guo, F. Vahid and W. Najjar -- Design of programmable interconnect for sublithographic programmable logic arrays / A. DeHon -- Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs / N. Campregher, P. Y. K. Cheung, G. A. Constantinides and M. Vasilko -- Soft error rate estimation and mitigation for SRAM-based FPGAs / G. Asadi and M. B. Tahoori -- Automated synthesis for asynchronous FPGAs / S. Peng, D. Fang, J. Teifel and R. Manohar -- Efficient static timing analysis and applications using edge masks / M. Hutton, D. Karchmer, B. Archell and J. Govig -- Evaluating heuristics in automatically mapping multi-loop applications to FPGAs / H. Ziegler and M. Hall -- Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability / Y. Lin, F. Li and L. He -- Combining low-leakage techniques for FPGA routing design / A. Lodi, L. Ciccarelli and R. Giansante -- Design, layout and verification of an FPGA using automated tools / I. Kuon, A. Egier and J. Rose -- Hyper customized processors for bio-sequence database scanning on FPGAs / T. Oliver, B. Schmidt and D. Maskell -- Efficient packet classification for network intrusion detection using FPGA / H. Song and J. W. Lockwood -- CUSP : a modular framework for high speed network applications on FPGAs / G. Schelle and D. Grunwald.

ISBN

1595930299

OCLC

• ocm59821877
• SCSB-5227837

Owning Institutions

Columbia University Libraries