Research Catalog

Title

FPGA 2006 : Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays : Hyatt Regency Monterey, Monterey, California, USA, February 22-24, 2006 / sponsored by ACM SIGDA ; with support from Actel, Altera, Synplicity, Trimberger Family Foundation, Xilinx.

Author

ACM International Symposium on Field-Programmable Gate Arrays (14th : 2006 : Monterey, Calif.)

Publication

New York : Association for Computing Machinery, [2006], ©2006.

Items in the Library & Off-site

Holdings

Details

Additional Authors

ACM Special Interest Group on Design Automation.

Description

viii, 240 pages : illustrations; 28 cm

Alternative Title

• Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
• International Symposium on Field-Programmable Gate Arrays
• FPGA '06

Subject

• Gate array circuits > Congresses
• Field programmable gate arrays > Congresses
• Programmable array logic > Congresses

Note

• "ACM order number 480060"--T.p. verso.

Bibliography (note)

• Includes bibliographical references and index.

Contents

A 90nm low-power FPGA for battery-powered applications / T. Tuan, S. Kao, A. Rahman, S. Das and S. Trimberger -- Embedded floating-point units in FPGAs / M. J. Beauchamp, S. Hauck, K. D. Underwood and K. S. Hemmert -- Measuring the gap between FPGAs and ASICs / I. Kuon and J. Rose -- Optimality study of logic synthesis for LUT-based FPGAs / J. Cong and K. Minkovich -- Improvements to technology mapping for LUT-based FPGAs / A. Mishchenko, S. Chatterjee and R. Brayton -- Improving performance and robustness of domain-specific CPLDs / M. Holland and S. Hauck -- Design, implementation, and verification of active cache emulator (ACE) / J. Hong, E. Nurvitadhi and S.-L. L. Lu -- Modeling the data-dependent performance of pattern-matching architectures / C. R. Clark and D. E. Schimmel -- An iterative division algorithm for FPGAs / J. Liu, M. Chang and C.-K. Cheng -- Yield enhancements of design-specific FPGAs / N. Campregher, P. Y. K. Cheung, G. A. Constantinides and M. Vasilko -- FPGA clock network architecture : flexibility vs. area and power / J. Lamoureux and S. J. E. Wilton -- Will power kill FPGAs? / M. Hutton, J. Rabaey, R. Vasishta, S. Knapp, G. Delp and V. Betz -- Performance benefits of monolithically stacked 3D-FPGA / M. Lin, A. El Gamal, Y.-C. Lu and S. Wong -- Magnetic tunnelling junction based FPGA / N. Brucho, L. Torres, G. Sassatelli and G. Cambon -- A reconfigurable architecture for hybrid CMOS/nanodevice circuits / D. B. Strukov and K. K. Likharev -- A reconfigurable hardware based embedded schedule for buffered crossbar switches / L. Mhamdi, C. Kachris and S. Vassiliadis -- An adaptive Reed-Solomon errors-and-erasures decoder / L. Atieno, J. Allen, D. Goeckel and R. Tessier -- A compact FPGA implementation of the hash function whirlpool / N. Pramstaller, C. Rechberger and V. Rijmen -- Armada : timing-driven pipeline-aware routing for FPGAs / K. Eguro and S. Hauck -- Combining module selection and resource sharing for efficient FPGA pipeline synthesis / W. Sun, M. J. Wirthlin and S. Neuendorffer -- Power-aware RAM mapping for FPGA embedded memory blocks / R. Tessier, V. Betz, D. Neto and T. Gopalsamy -- Application-specific customization of soft processor microarchitecture / P. Yiannacouras, J. G. Steffan and J. Rose -- Fast and accurate resource estimation of automatically generated custom DFT IP cores / P. A. Milder, M. Ahmad, J. C. Hoe and M. Puschel.

ISBN

1595932925

OCLC

• ocm69106477
• SCSB-5287554

Owning Institutions

Columbia University Libraries