Research Catalog

Title

Phase-locking in high-performance systems : from devices to architectures / edited by Behzad Razavi.

Publication

Piscataway, New Jersey : IEEE ; Hoboken, New Jersey : Wiley-Interscience, 2003.

Supplementary Content

• Contributor biographical information
• Publisher description

Items in the Library & Off-site

Holdings

Details

Additional Authors

Razavi, Behzad.

Description

xiii, 716 pages : illustrations; 29 cm

Subjects

• High performance computing
• Phase-locked loops

Note

• "A selected reprint volume."

Bibliography (note)

• Includes bibliographical references and index.

Contents

• Pt. I. Original Contributions -- Devices and Circuits for Phase-Locked Systems / B. Razavi -- Delay-Locked Loops - An Overview / C.-K. Ken Yang -- Delta-Sigma Fractional-N Phase-Locked Loops / I. Galton -- Design Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems / R. C. Walker -- Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers / K. S. Kundert -- Pt. II. Devices -- Physics-Based Closed-Form Inductance Expression for Compact Modeling of Integrated Spiral Inductors / S. Jenei, B. K. J. C. Nauwelaers and S. Decoutere -- The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's / J. R. Long and M. A. Copeland -- Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's / A. M. Niknejad and R. G. Meyer -- Stacked Inductors and Transformers in CMOS Technology / A. Zolfaghari, A. Chan and B. Razavi -- Estimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies / K. O -- A Q-Factor Enhancement Technique for MMIC Inductors / M. Danesh, J. R. Long, R. A. Hadaway and D. L. Harame -- On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's / C. Patrick Yue and S. S. Wong -- The Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors / S.-M. Yim, T. Chen and K. O -- Temperature Dependence of Q and Inductance in Spiral Inductors Fabricated in a Silicon-Germanium/BiCMOS Technology / R. Groves, D. L. Harame and D. Jadus -- Substrate Noise Coupling Through Planar Spiral Inductor / A. L. Pun, T. Yeung, J. Lau, F. J. R. Clement and D. K. Su -- Design of High-Q Varactors for Low-Power Wireless Applications Using a Standard CMOS Process / A.-S. Porret, T. Melly, C. C. Enz and E. A. Vittoz -- On the Use of MOS Varactors in RF VCO's / P. Andreani and S. Mattisson -- Pt. III. Phase Noise and Jitter -- Low-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks / J.Craninckx and M. Steyaert -- A Study of Phase Noise in CMOS Oscillators / B. Razavi -- A General Theory of Phase Noise in Electrical Oscillators / A. Hajimiri and T. H. Lee -- Physical Processes of Phase Noise in Differential LC Oscillators / J. J. Rael and A. A. Abidi -- Phase Noise in LC Oscillators / K. A. Kouznetsov and R. G. Meyer -- The Effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs / J. W. M. Rogers, J. A. Macedo and C. Plett -- Jitter in Ring Oscillators / J. A. McNeill -- Jitter and Phase Noise in Ring Oscillators / A. Hojimiri, S. Limotyrakis and T. H. Lee -- A Study of Oscillator Jitter Due to Supply and Substrate Noise / F. Herzel and B. Razavi -- Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise / P. Larsson -- On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops / B. R. Veillette and G. W. Roberts -- Pt. IV. Building Blocks -- A Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications / M. A. Margarit, J. L. Tham, R. G. Meyer and M. J. Deen -- A Fully Integrated VCO at 2 GHz / M. Zannoth, B. Kolb, J. Fenk and R. Weigel -- Tail Current Noise Suppression in RF CMOS VCOs / P. Andreani and H. Sjoland -- Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS / M. Tiebout -- Analysis and Design of an Optimally Coupled 5-GHz Quadrature LC Oscillator / J. van der Tang, P. van de Ven, D. Kasperkovitz and A. van Roermund -- A 1.57-GHz Fully Integrated Very Low-Phase-Noise Quadrature VCO / P. Vancorenland and M. S. J. Steyaert -- A Low-Phase-Noise 5GHz Quadrature CMOS VCO Using Common-Mode Inductive Coupling / S. L. J. Gierkink, S. Levantino, R. C. Frye and V. Boccuzzi -- An Integrated 10/5GHz Injection-Locked Quadrature LC VCO in a 0.18[mu]m Digital CMOS Process / A. Ravi, K. Soumyanath, L. R. Carley and R. Bishop -- Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology / J. Wood and S. Lipa -- 35-GHz Static and 48-GHz Dynamic Frequency Divider IC's Using 0.2-[mu]m AlGaAs/GaAs-HEMT's / Z. Lao, W. Bronner, A. Thiede, M. Schlechtweg, A. Hulsmann, M. Rieger-Motzer, G. Kaufel, B. Raynor and M. Sedler -- Superharmonic Injection-Locked Frequency Dividers / H. R. Rategh and T. H. Lee -- A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-[mu]m CMOS Technology / C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli and Z. Wang -- A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-[mu]m CMOS / J. Craninckx and M. S. J. Steyaert -- A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops / B. Chang, J. Park and W. Kirn -- High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler / P. Larsson -- A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC) / J. N. Soares, Jr. and W. A. M. Van Noije -- A Simple Precharged CMOS Phase Frequency Detector / H. O. Johansson -- Pt. V. Clock Generation by PLLs and DLLs -- A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation / V. von Kaenel, D. Aebischer, C. Piguet and E. Dijkstra -- A Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3 V/5 V Operation / H. C. Yang, L. K. Lee and R. S. Co -- Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques / J. G. Maneatis -- A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz / D. W. Boerstler -- A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL / S. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi and H. K. Lim -- Active GHz Clock Network Using Distributed PLLs / V. Gutnik and A. P. Chandrasakan -- A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control / J. Lee and B. Kim -- A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-[mu]m CMOS PLL Based on a Sample-Reset Loop Filter / A. Maxim, B. Scott, E. M. Schneider, M. L. Hagge, S. Chacko and D. Stiurca -- A Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines / Y.-J. Jung, S.-W. Lee, D. Shim, W. Kim and C. Kim -- An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance / Y. Moon, J. Choi, K. Lee, D.-K. Jeong and M.-K. Kim -- A Semidigital Dual Delay-Locked Loop / S. Sidiropoulos and M. A. Horowitz -- A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle / H.-H. Chang, J.-W. Lin, C.-Y. Yang and S.-I. Liu -- A Portable Digital DLL for High-Speed CMOS Interface Circuits / B. W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V. Tran, C. L. Portmann, D. Stark, Y.-F. Chan, T. H. Lee and M. A. Horowitz -- CMOS DLL-Base 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator / C. J. Foley and M. P. Flynn -- A 1.5V 86 mW/ch 8-Channel 622-3125-Mb/s/ch CMOS SerDes Macrocell with Selectable Mux/Demux Ratio / F. Yang, J. O'Neill, P. Larsson, D. Inglis and J. Othmer -- A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM / F. Lin, J. Miller, A. Schoenfeld, M. Ma and R. J. Baker -- A Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM / S. J. Kim, S. H. Hong, J.-K. Wee, J. H. Cho, P. S. Lee, J. H. Ahn and J. Y. Chung -- Pt. VI. RF Synthesis -- An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time / C. S. Vaucher -- A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers / W. S. T. Yan and H. C. Luong -- A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver / H. R. Rategh, H. Samavati and T. H. Lee -- A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-[mu]m CMOS Technology / C. Lam and B. Razavi -- Fast Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector / C.-Y. Yang and S.-I. Liu --
• Low-Power Dividerless Frequency Synthesis Using Aperture Phase Detection / A. R. Shahani, D. K. Shaeffer, S. S. Mohan, H. Samavati, H. R. Rategh, M. del M. Hershenson, M. Xu, C. P. Yue, D. J. Eddleman, M. A. Horowitz and T. H. Lee -- A Stabilization Technique for Phase-Locked Frequency Synthesizers / T.-C. Lee and B. Razavi -- A Modeling Approach for [Sigma]-[Delta] Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis / M. H. Perrott, M. D. Trott and C. G. Sodini -- A Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems / Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D.-K. Jeong and W. Kim -- A 1.1-GHz CMOS Fraction-N Frequency Synthesizer With a 3-b Third-Order [Sigma]-[Delta] Modulator / W. Rhee, B.-S. Song and A. Ali -- A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching / C.-H. Park, O. Kim and B. Kim -- A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation / M. H. Perrott, T. L. Tewksbury III and C. G. Sodini -- A CMOS Monolothic [Sigma][Delta]-Controlled Fractional-N Frequency Synthesizer for DSC-1800 / B. De Mauer and M. S. J. Steyaert -- Pt. VII. Clock and Data Recovery -- A 2.5-Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAN's and WAN's / K. Kishine, N. Ishihara, K. Takiguchi and H. Ichino -- Clock/Data Recovery PLL Using Half-Frequency Clock / M. Rau, T. Oberst, R. Lares, A. Rothermel, R. Schweer and N. Menoux -- A 0.5-[mu]m CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling / C.-K. K. Yang, R. Farjad-Rad and M. A. Horowitz -- A 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability / P. Larsson -- SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application / Y. M. Greshishchev and P. Schvan -- A Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate / Y. M. Greshishchev, P. Schvan, J. L. Showell, M.-L. Xu, J. J. Ojha and J. E. Rogers -- A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector / J. Savoj and B. Razavi -- A 10-Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection / J. Savoj and B. Razavi -- A 10-Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18[mu]m CMOS / J. E. Rogers and J. R. Long -- A 40-Gb/s Integrated Clock and Data Recovery Circuit in a 50-GHz f[subscript T] Silicon Bipolar Technology / M. Wurzer, J. Bock, H. Knapp, W. Zirwas, F. Schumann and A. Felder -- A Fully Integrated 40-Gb/s Clock and Data Recovery IC With 1:4 DEMUX in SiGe Technology / M. Reinhold, C. Dorschky, E. Rose, R. Pullela, P. Mayer, F. Kunz, Y. Baeyens, T. Link and J.-P. Mattia -- Clock and Data Recovery IC for 40-Gb/s Fiber-Optic Receiver / G. Georgiou, Y. Baeyens, Y.-K. Chen, A. H. Gnauck, C. Gropper, P. Paschke, R. Pullela, M. Reinhold, C. Dorschky, J.-P. Mattia, T. Winkler von Mohrenfels and C. Schulien.

ISBN

• 0471447277
• 9780471447276

LCCN

2003535257

OCLC

• ocm51933611
• SCSB-5464786

Owning Institutions

Columbia University Libraries