Research Catalog

Title

25 years of the International Symposia on Computer Architecture : selected papers / edited by Gurindar Sohi.

Author

International Symposium on Computer Architecture

Publication

New York : Association for Computing Machinery, 1998.

Items in the Library & Off-site

Details

Additional Authors

• Sohi, Gurindar
• Association for Computing Machinery

Description

xiii, 546 p. : ill.; 28 cm.

Alternative Title

• Twenty five years of the International Symposia on Computer Architecture
• Twenty-five years of the International Symposia on Computer Architecture

Subject

Computer architecture > Congresses

Genre/Form

Conference papers and proceedings

Bibliography (note)

• Includes bibliographical references.

Contents

• Banyan networks for partitioning multiprocessor systems / Jack Lipovski -- A preliminary architecture for a basic data flow processor / Jack B. Dennis -- Improving the throughput of a pipeline by insertion of delays / Janak H. Patel -- What we have learned from the PDP-11 / Gorden Bell and W.D. Strecker -- An instruction timing model of CPU performance / Leonard J. Shustek and Bernard L. Peuto -- High-level language computer architecture / David R. Ditzel and David A. Patterson -- Architecture of a massively parallel processor / Ken Batcher -- A processor for a high-performance personal computer / Ken Pier -- Lockup-free instruction fetch/prefetch Cache organization / David Kroft -- A study of branch prediction strategies / James E. Smith -- RISC I : a reduced instruction set computer / David A. Patterson and Carlo H. Séquin -- Decoupled access/execute architectures / J.E. Smith -- The NYU ultracomputer / Allan Gottlieb --^
• Using Cache memory to reduce processor-memory traffic / James R. Goodman -- Very long instruction word architectures and the ELI-512 / Joseph A. Fisher -- Characterization of processor performance in VAX-11/780 / Joel Emer and Douglas W. Clark -- A low-overhead coherence solution for multiprocessors with private Cache memories / Janak H. Patel -- Implementing precise interrupts in pipelined processors / J.E. Smith -- HPSm, a high performance restricted data flow architecture having minimal functionality / Wen-mei W. Hwu and Yale N. Patt -- The warp machines / Thomas Gross and Monica Lam -- Memory access buffering in multiprocessors / Michel Dubois and Christoph Scheurich -- Instruction issue logic for high-performance, interruptable pipelined processors / Gurindar S. Sohi -- The J-machine / William J. Dally [and others] -- On the inclusion properties for multi-level Cache hierarchies / Jean-Loup Baer and Wen-Hann Wang --^
• Evaluation of directory schemes for Cache coherence / John Hennessy -- Weak ordering : a new definition / Sarita V. Adve and Mark D. Hill -- Memory consistency and event ordering in scalable shared-memory multiprocessors / Kourosh Gharachorloo -- Improving direct-mapped Cache performance by the addition of a small fully-associative Cache and prefetch buffers / Norman P. Jouppi -- Monsoon / Gregory M. Papadopoulos and David E. Culler -- IMPACT : an architectural framwork for multiple-instruction issue / Wen-mei W. Hwu -- The DASH prototype / Daniel E. Lenoski and James P. Laudon -- Active messages / Thorsten von Eicken [and others] -- The turn model for adaptive routing / Lionel Ni -- Alternative implementations of two-level adaptive training branch prediction / Yale N. Patt and Tse-Yu Yeh -- The Cedar system / A. Veidenbaum [and others] -- Virtual memory mapped network interface for the SHRIMP multicomputer / Matthias A. Blumrich [and others] --^
• The Stanford FLASH multiprocessor / Jeffrey S. Kuskin -- Tempest and typhoon / Steven K. Reinhardt [and others] -- The MIT Alewife machine / Anant Agarwal -- Multiscalar processors / G.S. Sohi -- Simultaneous multithreading / Dean M. Tullsen [and others].

OCLC

• 39893176
• SCSB-13009443

Owning Institutions

Harvard Library