Research Catalog

Title

Proceedings of the IEEE 1997 Custom Integrated Circuits Conference : Westin Hotel, Santa Clara Convention Center, Santa Clara, California, May 5-8, 1997.

Author

Custom Integrated Circuits Conference (1997 : Santa Clara, Calif.)

Publication

New York, NY : Institute of Electrical and Electronics Engineers, ©1997.

Items in the Library & Off-site

Details

Additional Authors

• IEEE Electron Devices Society.
• IEEE Solid-State Circuits Council.

Description

606 pages : illustrations; 28 cm

Alternative Title

• 1997 IEEE Custom Integrated Circuits Conference
• CICC '97
• Custom Integrated Circuits Conference, 1997, proceedings of the IEEE 1997.

Subject

• Integrated circuits > Congresses
• Integrated circuits
• Circuits intégrés > Congrès
• Circuits intégrés à la demande > Congrès
• Réseaux neuronaux > Congrès

Genre/Form

Conference papers and proceedings.

Note

• "The CICC '97 is sponsored by the IEEE Electron Devices Society with cooperation from the IEEE Solid State Circuits Council".
• "97CH36005."

Bibliography (note)

• Includes bibliographical references and index.

Additional Formats (note)

• Also available in an electronic version.

Contents

• Welcome/Opening Remarks / Jane Buurma and Robert Cordell -- CCIC '96 -- Technical Program / Rakesh Kumar -- Keynote Address: Broadband Communications IC's: Enabling Wide Area Networking into the 21st Century / Henry Samueli -- High-Speed Continuous-Time Analog Complex Graphic Equalizer For Magnetic Recording Read Channels / J.C. Park, N.M. Zayed and L.R. Carley -- CMOS Analog Adaptive Equalizer for a DDS3 Tape Drive PRML Read Channel / J.S. Ignowski, R. Badyal and A. Brown -- Low Power 170MHz Discrete-Time Analog FIR Filter / X. Wang and R.R. Spencer -- Integrated 1.25 Gbit/s Laser Driver/Post Amplifier IC / S. Baumgartner, L. Freitag and M. Paschal -- Backside Optical Emission Diagnostics for Excess IDDQ / J.A. Kash, J.C. Tsang and R.F. Rizzolo -- Application of Circuit-Level Hot-Carrier Reliability Simulation to Memory Design / P.M. Lee, T. Seo and K. Ise -- ^ Whole-Chip ESD Protection Scheme for CMOS Mixed-Mode ICs in Deep-Submicron CMOS Technology / M.D. Ker, C.Y. Wu and H.H. Chang -- Performance Improvement of a Thick Field Oxide ESD Protection Circuit by Halo Implant / P.V. Gilbert, P.G.Y. Tsui and S.W. Sun -- 0.25 [mu]m CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with 5 to 400 MHz Lock Range / H. Sutoh, K. Yamakoshi and M. Ino -- CMOS Data and Clock Recovery Macrocell for Burst-Mode/Continuous-Mode Transmissions / N. Yamaoka, T. Taya and A. Yoshida -- Self-Calibration of Digital Phase-Locked Loops / B.R. Veillette and G.W. Roberts -- Fully Integrated LVD Clock Generation/Distribution IC / R. Emeigh and J. Strom -- Design of Sample-and-Hold Amplifiers for High-Speed Low-Voltage A/D Converters / B. Razavi -- 2-[mu]m, 1.6-mW Gated-g[subscript m] Sampler with 72 dB SFDR at 160 Ms/s and 320.25-MHz fi[subscript n] / S.C. Munroe and A.K. Lu -- ^
• Fully Differential 1.5V Low-Power CMOS Operational Amplifier with a Rail-to-Rail Current-Regulated Constant-g[subscript m] Input Stage / E. Peeters, M. Steyaert and W. Sansen -- 2.5 V Temperature Compensated CMOS Logarithmic Amplifier / K. Koli and K. Halonen -- 3V g[subscript m] C-Filter with On-Chip Tuning for CDMA / K. Halonen, S. Lindfors and J. Jussila -- Virtual Prototyping / J.A. Rowson -- Hardware/Software Partitioning Technique With Hierarchical Design Space Exploration / H. Oudghiri, B. Kaminska and J. Rajski -- Timing Abstraction of Intellectual Property Blocks / S.V. Venkatesh, R. Palermo and M. Mortazavi -- Novel Mixed-Signal Programmable Device with On-Chip Microprocessor / J. Faura, C. Horton I. and P. van Duong -- VSIA: It's Advantages from Four Different Perspectives / L.H. Cooke -- Hierarchical Decomposition Methodology for Single-Stage Clock Circuits / G. Ellis, L.T. Pileggi and R.A. Rutenbar -- Clock Methodology for High-Performance Microprocessors / K.M. Carrig, A.M. Chu and F.D. Ferraiolo -- Reliable Traversal Clock Delay Evaluation Including Input Slew Effect with 3D Parasitic Interconnect RLC Extraction / M. Lee, E. Chavez-reyes and E. Zorinsky -- CPU Controller Optimization in HDL Logic Synthesis / G. Yeap -- Automated Low-power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor / K. Usami, K. Nogami and M. Igarashi -- Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm / Y.M. Jiang, K.T. Cheng and A. Krstic -- EsteMate: A Tool for Automated Power and Area Estimation in Analog Top-Down Design and Synthesis / G. Van der Plas, J. Vandenbussche and G. Gielen -- Stochastic Wire Length Distribution for Gigascale Integration (GSI) / J. Davis, V. De and J. Meindl -- Compact Device Modelling for Circuit Simulation / C.C. McAndrew
• Circuit-level Simulation and Layout Optimization for Deep Submicron EOS/ESD Output Protection Device / T. Li, S. Ramaswamy and E. Rosenbaum -- Sparse Macromodeling Method for RC Interconnect Multiports / Y. Liu, L.T. Pileggi and A.J. Strojwas -- Integrated Circuit Technology Options for RFICs-Present Status and Future Directions / L.E. Larson -- 6.25-GHz Low DC Power Low-Noise Amplifier in SiGe / H. Ainspan, M. Soyuer and J.O. Plouchart -- 1.9 GHz Silicon Receiver with On-Chip Image Filtering / J. Macedo, M. Copeland and P. Schvan -- 2.4 GHz Monolithic Mixer for Wireless LAN Applications / K.L. Fong and R.G. Meyer -- 2.5-V, 1-W Monolithic CMOS RF Power Amplifier / D. Su and W. McFarland -- 2GHz Balanced Harmonic Mixer for Direct-Conversion Receivers / T. Yamaji and H. Tanimoto -- Design for Testability: Tunnelling Through The Test Wall / P.C. Maxwell -- Making Precise At-Speed Timing Measurements Via Boundary-Scan / T. Almy -- ^
• Power Consumption vs LO Amplitude for CMOS Colpitts Oscillators / Q. Huang -- New High Efficiency CMOS Voltage Doubler / P. Favrat, P. Deval and M.J. Declercq -- Dynamic Floating Body Control SOI CMOS Circuits for Power Managed Multimedia ULSIs / F. Morishita, M. Tsukude and K. Arimoto -- Novel Fully Programmable Switched-Current IIR Filter / M.O. Ahmad and S. Wang -- 250MHz Dual Port Cursor RAM using Dynamic Data Alignment Architecture / Y. Nakase, H. Kono and T. Tokuda -- Mixed-Signal Array Processor with Early Vision Applications / D.A. Martin, H.S. Lee and I. Masaki -- CMOS Binary Position-Sensitive Photodetector (PSD) Array / A. Makynen, T. Rahkonen and J. Kostamovaara -- Custom Analog Low Power Design: The Problem of Low Voltage and Mismatch / M. Steyaert, V. Peluso and J. Bastos -- High-Linearity Low-Voltage All-MOSFET Delta-Sigma Modulator / Y. Huang, G.C. Temes and H. Yoshizawa -- 2.4V, 700[mu]W, 0.18mm[superscript 2] Second-order Demodulator for High-Resolution [Sigma][Delta] DACs / Z. Shi, K. Hsu and O. Salminen -- 25Msps 8-bit/10Msps 10-bit CMOS Data Acquisition IC for Digital Storage Oscilloscopes / N. Kusayanagi, T. Choi and M. Hiwatashi -- 0.9V 5MS/s CMOS D/A Converter with Multi-Input Floating-Gate MOS / L.S.Y. Wong, C.Y. Kwok and G.A. Rigby -- 4-Channel Analog Front End for 25.6Mbps ATM Switches / K.L. Loh, S. Narayan and A. Kuo -- Transmitter and Receiver Interface Circuit Including an Equalizer and PFLL for 150Mbit/s Cable Communication / J. Routama, K. Koli and P.R. Ruhanen -- Wide Dynamic Range 1-k[Omega] Transimpedance Si Bipolar Preamplifier IC for 10-Gb/s Optical Fiber Links / T. Masuda, K.I. Ohhata and K. Imai -- 42 MB/S Multi-Channel Digital Adaptive Beamforming QAM Demodulator for Wireless Applications / J.Y. Lee, H.C. Liu and J.S. Putnam
• CMOS 10-Mbaud 20-mW PAM/QPSK Modulator Using A Digital-To-Analog Current-Division Waveshaping Converter / K. Choi and A. Buchwald -- Low Power and Compact Desktop ATM PMD, Y. Wakayama, F. Nakano / J. Takeuchi, N. Honda and K. Ishii -- Reusable Embedded DRAM Macrocell / P.W. Diodato, J.T. Clemens and W.W. Troutman -- P2Lib: Process-Portable Library and Its Generation System / H. Onodera, A. Hirata and T. Kitamura -- Dynamic Logic Synthesis / G. Yee and C. Sechen -- CMOS Current Steering Logic: Toward a Matured Technique for Mixed-Mode Applications / R.T.L. Saez, M. Kayal and M. Declercq -- Universal Guidelines for CMOS I/O Signal Integrity / T. Gabara, J. Harrington and R. Yan -- Full Function Verilog PLL Logic Model / M. Ashraf, T. Kellgren and M. Franz -- Verification of RF and Mixed-Signal Integrated Circuits for Substrate Coupling Effects / N.K. Verghese and D.J. Allstot -- Green Function Via Moment Matching For Rapid and Accurate Substrate Parasitics Evaluation / J. Zhao, W. Dai and R.C. Frye -- Analysis and Optimization of Monolithic Inductors and Transformers for RF ICs / A.M. Niknejad and R.G. Meyer -- Full-Chip Harmonic Balance / D. Long, R. Melville and K. Ashby -- Cyclostationary Noise Analysis of Large RF Circuits with Multi-tone Excitations / J. Roychowdhury, D. Long and P. Feldmann -- Evening Panel: "Smith-chart Meets Spice" a CAD Nightmare in RFIC Design" / Venu Gopinathan and Karti Mayaram -- Evening Panel: What Should It Cost to Test Your Chip? / Robert Aitken -- Evening Panel: Fab Capacity Forecasting: An Art or a Science? / Mike Beunder -- Challenges in the Design of Frequency Synthesizers for Wireless Applications / B. Razavi -- Fully Integrated Spiral-LC CMOS VCO Set with Prescaler for GSM and DCS-1800 Systems / J. Craninckx, M. Steyaert and H. Miyakawa -- Low-Noise 1.6-GHz CMOS PLL with On-Chip Loop Filter / J. Parker and D. Ray
• Level-Locked Loop, A Technique for Broadband Quadrature Signal Generation / S. Navid, F. Behbahani and A. Fotowat -- Micropower CMOS, Direct-Conversion, VLF Receiver Chip for Magnetic-Field Wireless Applications / D.M. Binkley, J.M. Rochelle and B.K. Swann -- TFSOI Technology for Portable Wireless Communications Systems / W.M. Huang, Y.C. Tseng and D. Monk -- Low-Voltage 0.35[mu]m CMOS/SOI Technology for High-Performance ASICs / A.O. Adan, T. Naka and S. Kaneko -- Micromachine-Based RF Low-Noise Voltage-Controlled Oscillator / D. Young and B. Boser -- Optimal Extrinsic Base Fabrication for High Performance SiGe HBTs for RF Communication Applications / R. Tang, J. Ford and B. Pryor -- System Module: A New Chip-On-Chip Module Technology / T. Mimura, T. Yoshida and K. Nagao -- ATM Application Specific Integrated Processor / A. Harasawa, T. Kaganoi and T. Kanoh -- Single-Chip Controller for 1.2 Gbps Shared Buffer ATM Switches / N. Mizukoshi, R. Fan and H. Suzuki -- Skew Tolerant CMOS Level-Based ATM Data-Recovery System Without PLL Topology / S. Gogaert and M. Steyaert -- 50 MHz 16-Point FFT Processor for WLAN Applications / N. Weste, M. Bickerstaff and T. Arivoli -- 4*2.5Mchip/s Direct Sequence Spread Spectrum Receiver with Digital IF and Integrated ARM6 Core / B. Gyselinckx, L. Rynders and M. Engels -- Transversal Equalizer with an Increased Adaptation Speed and Tracking Capability / C. Lutkemeyer and T.G. Noll -- VLSI Implementation of a 200-MHz 16x16 Left-to-Right Carry-Free Multiplier in 0.35 [mu]m CMOS Technology for Next-Generation DSPs / R. Kolagotla, H.R. Srinivas and G.F. Burns -- Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits / J.P. Halter and F.N. Najm -- Clock-Gating and Its Application to Low Power Design of Sequential Circuits / Q. Wu, X. Wu and M. Pedram -- High-Level Area Prediction for Power Estimation / M. Nemani and F.N. Najm
• Sensitivity of Power Dissipation to Uncertainties in Primary Input Specification / Z. Chen, K. Roy and T. L. Chou -- Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and 3-D Simulation / D. Sylvester, J. C. Chen and C. Hu -- Nonlinear Settling Behavior in Oversampled Converters / F. Wang and R. Harjani -- Efficient Monte-carlo Thermal Noise Simulation For [Sigma][Delta] Modulators / Y. Dong and A. Opal -- Overview of Computer-Aided Analysis Tools for RFIC Simulation: Algorithms, Features and Limitations / K. Mayaram, D. C. Lee and S. Moinian -- Inductorless 900MHz RF Low-Noise Amplifier in 0.9[mu]m CMOS / Y. J. Shin and K. Bult -- 2V, Low Power, Single-Ended 1GHz CMOS Direct Upconversion Mixer / M. Borremans and M. Steyaert -- BiCMOS Double-Low-IF Receiver for GSM / M. Banu, H. Wang and M. Seidel -- Fully-Integrated 5MHz-IF Digital FM Demodulator / M. Song, J. Park and E. Joe -- Completely Integrated Single-Chip PLL with a 34 GHz VCO Using 0.2[mu]m E-/D-HEMT-Technology / M. Lang, P. Leber and Z. G. Wang -- High Performance, High Density Sea of Modules FPGA Architecture / K. El-Ayat, S. Kaptanoglu and R. Chan -- 3.3-V Programmable Logic Device that Addresses Low Power Supply and Interface Trends / R. Patel, W. Wong and J. Lam -- New Synthesis Efficient, High Density and High Speed ORCA FPGA / S. Singh, B. Britton and C. Spivak -- 5.1ns, 5000 Gate, CMOS PLD with Selectable Frequency Multiplication and In-System Programmability / J. Costello, J. Balicki and V. Bocchino -- Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size / V. Betz and J. Rose -- Field Programmable Analog Array and Its Application / D. Anderson, C. Marcjan ̃and D. Bersch -- Quick Placement with Geometric Constraints / E. Malavasi, J. L. Ganley and E. Charbon -- ^ Multi-layer Over-the-Cell Routing with Obstacles / H. P. Tseng and C. Sechen
• Effective Routing Methodology for Gb/s LSI using Deep Submicron CMOS/SIMOX Technology / T. Watanabe, Y. Ohtomo and K. Yamakoshi -- Congestion-Driven Placement Improvement Algorithm for Large Scale Sea-of-Gates Arrays / T. Sadakane, H. Shirota and K. Takahasi -- Techniques For Aggressive Supply Voltage Scaling and Efficient Regulation / A. Dancy and A. Chandrakasan -- 300MIPS/W RISC Core Processor with Variable Supply-Voltage Scheme in Variable Threshold-Voltage CMOS / K. Suzuki, S. Mita and T. Fujita -- Transistor Sizing for High Performance and Low Power / J.P. Fishburn and S. Taneja -- IO Buffer For High Performance, Low-Power Applications / J.S. Shor, Y. Afek and E. Engel -- 1.5-V 3-mW 10-bit 50-MS/s CMOS DAC with Low Distortion and Low Intermodulation in Standard Digital CMOS Process / N. Tan -- 0.24 mW, 14.4 kbps, r=1/2, k=9 Viterbi Decoder / I. Kang and A.N. Willson, Jr.

ISBN

• 0780336690
• 9780780336698
• 0780336704
• 9780780336704
• 0780336712
• 9780780336711

OCLC

• ocm37281364
• 37281364
• SCSB-2131142

Owning Institutions

Princeton University Library