Research Catalog

Title

Proceedings of the IEEE 1994 Custom Integrated Circuits Conference : Town & Country Hotel, San Diego, California, May 1-4, 1994 / sponsored by the IEEE Electron Devices Society, and the IEEE Solid-State Circuits Council.

Author

Custom Integrated Circuits Conference (1994 : San Diego, Calif.)

Publication

New York, NY : Institute of Electrical and Electronics Engineers ; Piscataway, NJ : IEEE Order Dept., ©1994.

Items in the Library & Off-site

Details

Additional Authors

• IEEE Electron Devices Society.
• IEEE Solid-State Circuits Council.
• Institute of Electrical and Electronics Engineers.

Description

670 pages : illustrations; 28 cm

Alternative Title

• 1994 IEEE Custom Integrated Circuits Conference
• CICC '94
• Custom Integrated Circuits Conference, 1994, proceedings of the IEEE 1994.

Subject

• Integrated circuits > Congresses
• Integrated circuits
• Circuits intégrés > Congrès
• Circuits intégrés à la demande > Congrès
• Réseaux neuronaux > congrès

Genre/Form

Conference papers and proceedings.

Note

• Sponsored by the IEEE Electron Devices Society with cooperation from the IEEE Solid State Circuits Council.
• Cover and spine title: 1994 IEEE Custom Integrated Circuits Conference.
• "94CH3427-2."

Bibliography (note)

• Includes bibliographical references and index.

Additional Formats (note)

• Also available in an electronic version.

Contents

• Welcome/Opening Remarks / Lauren Christopher and Resve Saleh -- CICC '94 -- Technical Program / Allen Barlow -- Keynote Address: Digital Wireless: Computer and Communication Symbiosis or Culture Clash? / Andrew J. Viterbi -- CMOS Technology for Low Voltage/Low Power Applications / B. Davari, R. Dennard and G. Shahidi -- High Performance 3.3 and 5 Volt 0.5-[mu]m CMOS Technologies for ASICs / I. Kizilyalli, M. Thoma, S. Lytle, E. Martin, S. Vitkavage, R. Singh, P. Bechtold, J. Kearney, M. Rambaud, A. Oates, V. Ryan, P. Layman, M. Twiford and W. Cochran -- BEST2 -- A High Performance Super Self-Aligned 3V/5V BiCMOS Technology With Extremely Low Parasitics for Low-Power Mixed-Signal Applications / J. Sung, T. Chiu, K. Lau, T. Liu, V. Archer, B. Razavi, R. Swartz, F. Erceg, J. Glick, G. Hower, S. Krafty, A. LaDuca, M. Ling, K. Moerschel, W. Possanza, M. Prozonic and T. Long -- Trends in Devices for Low Power
• Chip Set for 7 KHz Handfree Telephony / P. LeScan, M. Soler, F. Perreal, G. Martel, F. Closse, F. Balestro, P. Senn, D. Morche, J. Jullien and G. Le Tourneur -- Overview of Technology, Architecture and CAD Tools for Programmable Logic Devices / S. Brown -- RRANN: The Run-Time Reconfiguration Artificial Neural Network / J. Eldredge and B. Hutchings -- FPGA Implementation of FIR Filters Using Pipelined Bit-Serial Canonical Signed Digit Multipliers / S. He and M. Torkelson -- Using FPGAs to Prototype a Self-Timed Floating Point Co-Processor / J. Novak and E. Brunvand -- Single Chip Multimedia Video Processor / K. Balmer, N. Ing-Simmons, P. Moyse, I. Robertson, J. Keay, M. Hammes, E. Oakland, R. Simpson, G. Barr and D. Roskell -- 1.5 GIPS Video Signal Processor (VSP) / H. Veendrick, O. Popp, G. Postuma and M. Lecoutere -- 1.2 GIP General Purpose Digital Image Processor / S. Evans, S. Walker, N. Thacker, R. Yates and P. Ivey -- Data Flow Processor for Multi-Standard Video Codec / B. Lee, H. Kwon, B. Kim, D. Still, I. Kopet and S. Magar -- 162Mbit/s Variable Length Decoding Circuit Using an Adaptive Tree Search Technique / Y. Ooi, A. Taniguchi and S. Demura -- Multipurpose Scanning Rate Converter IC for Improved Quality Television / V. D'Alto, C. Heintz, M. Karlsson, A. Cremonesi, A. Vindigni and S. Dal Poz -- Low Cost Application Specific Video Codec for Consumer Video Phone / S. Azim, M. Jahanghir, R. Aghevli, C. Holmqvist, J. Mena, M. Takla, M. Yellayi, B. Edwards, N. Weste and V. Maheshwari -- EDA and Electronic System Design / J. Rowson -- Improving Cell Libraries for Synthesis / K. Scott and K. Keutzer -- Automatic Synthesis and the Cost of Testing / T. Marchok and W. Maly -- State Assignment for Low Power Dissipation / L. Benini and G. DeMicheli -- State Assignment for Low-Power FSM Synthesis Using Genetic Local Search / E. Olson and S. Kang
• Working Chips from High Level Synthesis: A Case Study from Industry / R. Hunter, T. Fuhrman and D. Thomas -- Radio Frequency Integrated Circuits for Portable Communications / A. Abidi -- Low Noise Integrated AMPS IF Filter / T. Adachi, A. Ishikawa, K. Tomioka, S. Hara, K. Takasuka, H. Hisajima and A. Barlow -- 10.7MHz Bandpass Delta-Sigma A/D Modulators / F. Singor and M. Snelgrove -- Versatile Monolithic 800kHz to 800MHz Phase-Startable Oscillator / L. Dobos and B. Jensen -- Low Noise CMOS Frequency Synthesizer with Dynamic Bandwidth Control / M. Bayer, T. Chomicz, F. James, P. McEntarfer, D. Mijuskovic and J. Porter -- Low Power Programmable Logic Device Reconfigurable for 3.3V or 5.0V Operation During and After Fabrication / C. McClintock, W. Leong, H. Randhawa and J. Watson -- Minimizing Interconnection Delays in Array-based FPGAs / M. Khellah, S. Brown and Z. Vranesic -- Programming Antifuses in Crosspoint's FPGA / D. Marple and L. Cooke -- SIPPOS (Single Poly Pure CMOS) EEPROM Embedded FPGA by News Ring Interconnection and Highway Path / K. Ohsaki, N. Asamoto and Y. Takaya -- Novel Reprogrammable Interconnect Architecture with Decoded RAM Storage / R. Guo, H. Nguyen, A. Srinivasan, Q. Nasir, H. Cai, S. Law and A. Mohsen -- Architectures for a Real Time Classification Processor / M. Robert, P. Gorria, J. Miteran and S. Turgis -- High Performance Multi-Channel Data Compression Chip / E. Nusinov and J. Pasco-Anderson -- Fast Single Chip Implementation of 8192 Complex Points / E. Bidet, C. Joanblanq and P. Senn -- Single Chip QCELP Vocoder for CDMA Digital Cellular / J. McDonough, C. Chang, P. Kantak, C. Sakamaki, R. Singh and M. Tsai -- 180 MHz 16 bit Multiplier Using Asynchronous Logic Design Techniques / R. Burford, X. Fan and N. Bergmann -- Programmable Digital Signal Processor for Service Adaptive Access / D. Mitchler and S. Aly
• Flexible 8-channel Data Acquisition Device for Signal Processing and Analysis / D. McGrath, J. Krisciunas and S. Garverick -- Real-Time Object Extraction Processor / R. Nishimura, T. Kinugasa, H. Komatsu, J. Kamimura and I. Imaide -- Synthesizing Optimal Registerfile Architectures for FPGA Technology / C. Gebotys -- ILP Synthesis of Signal Processing Architectures with Minimum Structural Complexity / B. Haroun and B. Sajjadi -- Generating the Optimal Graph Representations from the Instruction Set Tables of Circuits / C. Chen and W.-C. Tseng -- Skew and Delay Minimization of High Speed CMOS Circuits Using Stochastic Optimization / S. Mehrotra, P. Franzon and W. Liu -- Power Analysis for Semi-Custom Design / B. George, G. Yeap, M. Wloka, S. Tyler and D. Gossain -- POP: an efficient Performance OPtimization algorithm based on integrated approach / H. Chang and J. Abraham -- Design of Portable Systems / A. Chandrakasan, A. Stratakos, R. Brodersen and R. Allmon -- Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation / S. Sun and P. Tsui -- Self-Adjusting Threshold-Voltage Scheme (SATS) For Low-Voltage High-Speed Operation / T. Kobayashi and T. Sakurai -- High Sensitivity, Low Power, Silicon Magnetic Field Detector / J. Doyle and C. Lyden -- High Speed, Low Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications / A. Parameswar, H. Hara and T. Sakurai -- Adiabatic Dynamic Logic / A. Dickinson and J. Denker -- Yield Enhancement Prediction with Statistical Process Simulations in an Advanced Poly-Emitter Complementary Bipolar Technology / J. Lopez-Serrano, S. Koh, T. Crandell, J. Delgado, H. Nicolay, T. Haycock and A. Strojwas -- Parametric Yield Prediction of Complex, Mixed-Signal ICs / M. O'Leary and C. Lyden
• Applying a Submicron Mismatch Model to Practical IC Design / C. Guardiani, A. Tomasini, J. Benkoski, M. Quarantelli and P. Gubian -- Performance Modeling of Analog Circuits Using Additive Regression Splines / C. Chao and L. Milor -- Moment Method for Statistical Analysis of High Speed VLSI Interconnects / L. Li, Q. Zhang and M. Nakhla -- Manufacturability Analysis Environment -- MAPEX / H. Heineken and W. Maly -- Component Level Yield/Cost Model for Predicting VLSI Manufacturability on Designs Using Mixed Technologies, Circuitry, and Redundancy / S. Domer, S. Foertsch and G. Raskin -- IC Design Considerations for the Harsh Automotive Electrical Environment / D. Laude -- Dedicated Protective Functions of Automotive ICs and Design Examples / A. Lechner, D. Draxelmayr, H. Irmer, H. Zitta and J. Melbert -- Portable 3-Axis 11-Bit Shock Measurement Circuit / B. DeGeeter, M. Pierre, O. Nys, V. von Kaenel, M. Chevroulet and M. Degrauwe -- Low Power Transponder IC for High Performance Identification Systems / U. Kaiser and W. Steinhagen -- Silicon Range Finder -- A Realtime Range Finding VLSI Sensor / K. Sato, A. Yokoyama and S. Inokuchi -- Maximum Entropy Co-Processor for Computed Tomography / S. Chang, M. Peckerar and C. Marrian -- Analog Hardware Description Languages / R. Saleh, D. Rhodes, E. Christen and B. Antao -- Capture and Re-use of Analog Simulation Knowledge / R. Henderson, M. Hinners, P. Nussbaum and L. Astier -- DORIC: Design of Optimal & Robust Integrated Circuits / Z. Daoud and C. Spanos -- Analog Circuit Synthesis for Large, Realistic Cells: Designing a Pipelined A/D Converter with ASTRX/OBLX / E. Ochotta, L. Carley and R. Rutenbar -- Top-Down, Constraint-Driven Design Methodology Based Generation of n-bit Interpolative Current Source D/A Converters / H. Chang, E. Liu, R. Neff, E. Felt, E. Malavasi, E. Charbon, A. Sangiovanni-Vincentelli and P. Gray
• Methodology for Analog High-Level Synthesis / S. Donnay, K. Swings, G. Gielen and W. Sansen -- All-CMOS Architecture for a Low-Power Frequency- Hopped 900 MHz Spread Spectrum Transceiver / J. Min, A. Rofougaran, H. Samueli and A. Abidi -- 1.2[mu]m CMOS Implementation of a Low-Power 900-MHz Mobile Radio Frequency Synthesizer / M. Thamsirianunt and T. Kwasniewski -- 1.57 GHz Asynchronous and 1.4 GHz Dual-Modulus 1.2[mu]m CMOS Prescalers / R. Rogenmoser, Q. Huang and F. Piazza -- 0.7-mW/2-GHz Dual Modulus Prescaler IC / Y. Nakasha, T. Miyata, Y. Watanabe, H. Ochimizu, S. Kuroda and M. Takikawa -- Analog/Digital Interface for Cellular Telephony / N. van Bavel, P. Maulik, K. Albright and X.-M. Gong -- Integrated [pi]/4-Shift QPSK Baseband Modulator / Y. Kobayashi, T. Hida, K. Sawada, K. Hodohara, Y. Ueda, K. Takasuka and A. Barlow -- I[subscript DDQ] Testing on a Custom Automotive IC / S. Mallarapu and A. Hoffman -- ^ Diagnosing CMOS Bridging Faults with Stuck-At. IDDQ, and Voting Model Fault Dictionaries / S. Millman and J. Acken -- Analog Testability Analysis and Fault Diagnosis using Behavioral Modeling / E. Liu, W. Kao, E. Felt and A. Sangiovanni-Vincentelli -- Circuit Partitioning for Pipelined Pseudo-Exhaustive Testing Using Simulated Annealing / H.-Y. Liou, T.-T. Lin, L.-T. Liu and C.-K. Cheng -- iRULE: Fast Hot-Carrier Reliability Diagnosis Using Macro-Models / C. Teng, W. Sun, S. Kang, P. Fang and J. Yue -- Slope Considerations in Probabilistic Simulation / G. Stamoulis and I. Hajj -- Improved Estimation of the Switching Activity for Reliability Prediction in VLSI Circuits / F. Najm -- Benchmark Circuits for Mixed-Mode Simulators / R. Saleh, S. Jou, D. Overhauser, X. Xu and Y. Wang -- Behavioral Simulation for Analog System Design Verification / B. Antao and A. Brodersen -- Behavioral Simulation Techniques for Phase/Delay-Locked Systems / A. Demir, E. Liu, A. Sangiovanni-Vincentelli and I. Vassiliou
• Fully Symbolic Analysis of Large Analog Integrated Circuits / J. Hsu and C. Sechen -- Efficient Symbolic Computation of Approximated Small-Signal Characteristics / P. Wambacq, F. Fernandez, G. Gielen and W. Sansen -- Automated Load-Independent Cell Library Macromodeling for Efficient and Accurate Waveform Simulation / D. Ciplickas and R. Rohrer -- Micro Systems Technology / J. Fluitman -- Advanced High Performance CCD Technology for a 1/4-Inch 560k Pixel IT-CCD Image Sensor / S. Terakawa, Y. Sano, T. Imanishi and Y. Hiroshima -- Improved Reliability of Amorphous Silicon Anti-Fuse Used in High Speed FPGA / S. Nariani, C. Gabriel and V. Jam -- Advanced CMOS EPROM Technology for High Speed/High Density Programmable Logic Devices and Memory Applications / G. Hu, R. Madurawe, M. Cleeves, A. Dejenfelt, C. Pass, M. Carpenter, P. Zicolello, C. Malmfeldt and K. Norman -- 85-mW, 10-bit 40-MS/s ADC with Decimated Parallel Architecture, K. Nakamura / M. Hotta, R. Carley and D. Allstot -- 10-bit, 20-MS/s, 35-mW Pipeline A/D Converter / T. Cho and P. Gray -- Parallel Delta-Sigma A/D Conversion / E. King, F. Aram, T. Fiez and I. Galton -- Active Compensation of Parasitic Capacitances in a 10-bit 50 MHz CMOS D/A Converter / S. Brigati, G. Caiulo, F. Maloberti and G. Torelli -- 130[mu]W DAC for Low-Power Video Systems / D. Nairn -- 12 bit 1MHz ADC with 1mW Power Consumption / K. Satou, K. Tsuji, M. Sahoda, H. Otsuka, K. Mori and T. Iida -- Low Power 20 Bit Instrumentation Delta-Sigma ADC / K. Yamamura, A. Nogi and A. Barlow -- Imposing Tight Specifications on Analog ICs Through Simultaneous Placement and Module Optimization / E. Charbon, E. Malavasi, D. Pandini and A. Sangiovanni-Vincentelli -- Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT / S. Mitra, R. Rutenbar, L. Carley and D. Allstot
• Mixed-Signal Noise-Decoupling via Simultaneous Power Distribution Design and Cell Customization in Rail / B. Stanisic, R. Rutenbar and L. Carley -- LAYIN: Toward a Global Solution for Parasitic Coupling Modeling and Visualization / F. Clement, E. Zysman, M. Kayal and M. Declercq -- Transistor Size Optimization in Layout Design Rule Migration / S. Kishida, Y. Shibayama, H. Tanizaki, A. Hanami and I. Ohkura -- Compaction with Shape Optimization / K. Okada, H. Onodera and K. Tamaru -- Interconnect Design Using Convex Optimization / P. Sancheti and S. Sapatnekar -- 1.5% Jitter PLL Clock Generation System for a 500-MHz RISC Processor / H. Igura, K. Suzuki, T. Nakayama, M. Izumikawa, M. Nomura, J. Goto, T. Inoue, H. Abiko, K. Okabe, A. Ono, M. Yamashina and H. Yamada -- PLL Timing Design Techniques for Large-scale, High-speed, Low-power, and Low-cost SRAMS / K. Nakamura, S. Kuhara, T. Kimura, M. Takada, H. Suzuki, H. Yoshida and T. Yamazaki -- "GaAs on Si" PLL Frequency Synthesizer IC using Chip on Chip Technology / S. Sekine, K. Takada, H. Suzuki, K. Kodama, S. Moriya and M. Kubota -- Digitally-Programmable Analog Cells for Artificial Neural Networks / A. Passos Almeida and J. Franca -- Programmable Analogue CMOS Chip for High Speed Image Processing Based on Cellular Neural Networks / P. Kinget and M. Steyaert -- Design and Optimization of High Voltage Analog and Digital Circuits Built in a Standard 5V CMOS Technology / H. Ballan, M. Declercq and F. Krummenacher -- 50-V LCD Driver Integrated in Standard 5-V CMOS Process / V. Valencic, H. Ballan, P. Deval, B. Hochet and M. Declercq -- Embedded Memory Design for a Four Issue Superscaler RISC Microprocessor / T. Takayanagi, K. Sawada, T. Sakurai, Y. Parameswar, S. Tanaka, N. Ikumi, M. Nagamatsu, Y. Kondo, K. Minagawa, J. Brennan, P. Hsu, P. Rodman, J. Bratt, J. Scanlon, M. Tang, C. Joshi and M. Nofal
• 180MHz Multiple-Registered DRAM for Low-cost 2MB/chip Secondary Cache / H. Iwamoto, N. Watanabe, A. Yamazaki, S. Sawada, Y. Murai, Y. Konishi, H. Itoh, T. Miyamoto and M. Kumanoya -- 400MHz, 300mW, 8kb, CMOS SRAM Macro with a Current Sensing Scheme / M. Izumikawa, K. Suzuki, M. Nomura, H. Igura, H. Abiko, K. Okabe, A. Ono, T. Nakayama, M. Yamashina and H. Yamada -- 4.4-ns CMOS 54x54-b Multiplier Using Pass-transistor Multiplexer / N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki and Y. Nakagome -- Lean Integration: Achieving a Quantum Leap in Performance and Cost of Logic LSIs / K. Yano, Y. Sasaki, K. Rikino and K. Seki -- 0.5 micron Low-Power BiCMOS Gate Array for B-ISDN 622 Mb/s User-Network Interface / Y. Hayakawa, T. Hanibuchi, K. Sawada, M. Ueda, K. Suda and S. Kato -- GaAs HBT Gate Array For High Performance ASICs / S. Yinger, F. Lee, R. Huang, K. Schneider, E. Wang, K. Smith, M. Penugonda, S. Jacobs and T. Carter -- Silicon Bipolar Chipset for SONET/SDH 10 Gbit/s Fiber-Optic Links / I. Andersson, B. Rudberg, T. Lewin, M. Reed, S. Planer and S. Sundaram -- 20 Gb/s 2:1 Data Selector / J. Doernberg and A. Armstrong -- Monolithic 625Mb/s Data Recovery Circuit in 1.2[mu]m CMOS / J. Kang, W. Liu and R. Cavin -- Wide-Dynamic-Range and Extremely High-Sensitivity CMOS Optical Receiver IC Using Feed-Forward Auto-Bias Adjustment / M. Nakamura, N. Ishihara, Y. Akazawa and H. Kimura -- Low Power 11x320Mbps Parallel Transmitter/Receiver LSIs for 2.4Gbps Optical Link / T. Kamei, N. Miyahara, T. Taya and S. Yamaoka -- Efficient Self-Timed Queue Architecture for ATM Switch LSIs / H. Kondoh, H. Yamanaka, M. Ishiwaki, Y. Matsuda and M. Nakaya -- Three-Layer Channel Routing for Standard Cells with Column-Dependent Variable Over-the-Cell Routing Capacities / T. Koide, M. Tsuchiya, S. Wakabayashi and N. Yoshida -- New Triple-Layer OTC Channel Router / J. Kim and S. Kang
• New Efficient Routing Method for Channel-less Sea-of-Gates Arrays / M. Terai, K. Takahashi, H. Shirota and K. Sato -- Performance-Driven Routing Approach for Thick Film MCMs / Q. Yu, B. Sandeep, J. Lai and N. Sherwani -- Circuit Partitioning Under Capacity and I/O Constraints / M. Shih and E. Kuh -- Minimum Delay Placement with Influence of Nets and Hierarchical Clustering / M. Tanaka, Y. Miyazawa, H. Aizawa and M. Minowa -- Multi-Port RAM Generator with Novel Memory Cell for CMOS Sea-of-Gates / K. Nii, H. Maeno, T. Osawa and S. Iwade.

ISBN

• 0780318862
• 9780780318861
• 0780318870
• 9780780318878
• 0780318889
• 9780780318885

OCLC

• ocm30826042
• 30826042
• SCSB-2021335

Owning Institutions

Princeton University Library