Research Catalog

Title

12th IEEE VLSI Test Symposium : April 25-28, 1994, Cherry Hill, New Jersey : proceedings / sponsored by IEEE Computer Society Technical Committee on Test Technology, IEEE Philadelphia Section.

Author

IEEE VLSI Test Symposium (12th : 1994 : Cherry Hill, N.J.)

Publication

Los Alamitos, Calif. : IEEE Computer Society Press, ©1994.

Items in the Library & Off-site

Details

Additional Authors

• IEEE Computer Society. Test Technology Technical Committee.
• Institution of Electrical and Electronics Engineers. Philadelphia Section.

Description

xviii, 466 pages : illustrations; 28 cm

Alternative Title

• Twelfth IEEE VLSI Test Symposium
• VLSI Test Symposium, 1994, proceedings, 12th IEEE.

Subject

• Integrated circuits > Very large scale integration > Testing > Congresses
• Integrated circuits > Very large scale integration > Testing
• Circuits intégrés à très grande échelle > Expériences > Congrès

Genre/Form

Conference papers and proceedings.

Bibliography (note)

• Includes bibliographical references and index.

Contents

• "Historical Observations on Design, Testing and Error Control of Digital Computer Systems" / Irving Reed -- Synthesizing Designs with Low-Cardinality Minimum Feedback Vertex Set for Partial Scan Application / S. Dey, M. Potkonjak and R.K. Roy -- On Identifying Undetectable and Redundant Faults in Synchronous Sequential Circuits / I. Pomeranz and S.M. Reddy -- Delay-Fault Testability Preservation of the Concurrent Decomposition and Factorization Transformations / A. El-Maleh and J. Rajski -- Design of Fully Testable Circuits by Functional Decomposition and Implicit Test Pattern Generation / B. Steinbach and M. Stockert -- Retiming Sequential Circuits to Enhance Testability / S. Dey and S.T. Chakradhar -- New Strategy for Testing Analog Filters / D. Vazquez, A. Rueda and J.L. Huertas -- Design-for-Test Technique for Switched-Capacitor Filters / M. Soma and V. Kolarik -- Design for Diagnosability of Linear Digital Filters Using Time-Space Expansion / A. Chatterjee and R.K. Roy -- Multifrequency Testability Analysis for Analog Circuits / M. Slamani and B. Kaminska -- BIST Technique for a Frequency Response and Intermodulation Distortion Test of a Sigma-Delta ADC / M.F. Toner and G.W. Roberts -- Design for Testability Technique for Test Pattern Generation with LFSRs / D. Kagaris and S. Tragoudas -- Test Embedding with Discrete Logarithms / M. Lempel, S.K. Gupta and M.A. Breuer -- Multiple Weighted Cellular Automata / D.J. Neebel and C.R. Kime -- Structural Constraints for Circular Self-Test Paths / J. Carletta and C. Papachristou -- Aliasing Error for a Mask ROM Built-In Self-Test / K. Iwasaki, A. Furuta and S. Nakamura -- Discrete Test Generation by Continuous Methods / I. Rivin and S.T. Chakradhar -- ICAT: Incremental Combinational ATPG / B.S. So and C.R. Kime
• Test Generation and Three-State Elements, Busses, and Bidirectionals / J.T. van der Linden, M.H. Konijnenburg and A.J. van de Goor -- Functional Learning: A New Approach to Learning in Digital Circuits / R. Mukherjee, J. Jain and D.K. Pradhan -- Diagnostic Simulation of Stuck-At Faults in Combinational Circuits / S. Chakravarty and Y. Gong -- Novel Architectures for TSC/CD and SFS/SCD Synchronous Controllers / S.M. Kia and S. Parameswaran -- Controllable Self-Checking Checkers for Conditional Concurrent Checking / S. Tarnick -- Code Disjoint Self-Parity Combinational Circuits for Self-Testing, Concurrent Fault Detection and Parity Scan Design / M. Goessel and E.S. Sogomonyan -- Efficient UBIST for RAMS / M. Nicolaidis -- On-Line Delay Testing of Digital Circuits / P. Franco and E.J. McCluskey -- Coverage Metrics for Functional Tests / J.R. Wallack and R. Dandapani -- ^ On the Complexity of Terminal Stuck-at Fault Detection Tests for Monotone Boolean Functions / V.A. Vardanian -- Limitations in Predicting Defect Level Based on Stuck-at Fault Coverage / J. Park, M. Naivar, R. Kapur, M.R. Mercer and T.W. Williams -- Correlating Defect Level to Final Test Fault Coverage for Modular Structured Designs / T.J. Powell, K.M. Butler, M. Ales, R. Haley and M. Perry -- Quality Impacts of Non-Uniform Fault Coverage / P.C. Maxwell -- On Compacting Test Sets by Addition and Removal of Test Vectors / S. Kajihara, I. Pomeranz, K. Kinoshita and S.M. Reddy -- Neural Models for Transistor and Mixed-Level Test Generation / C.L.C. Cooper and M.L. Bushnell -- New Functional Fault Model for System-Level Descriptions / P. Camurati, F. Corno, M. Meo and P. Prinetto -- Sequential Test Generation with Reduced Test Clocks for Partial Scan Designs / S.Y. Lee and K.K. Saluja -- ^ Speeding Up Behavioral Test Pattern Generation Using an Alorithmic Improvement / L. Vandeventer, J.F. Santucci and N. Giambiasi
• Power Supply Ramping and Current Measurement Based Technique for Analog Fault Diagnosis / S.S. Somayajula, E. Sanchez-Sinencio and J. Pineda de Gyvez -- Architecture of Test Support ICs for Mixed-Signal Testing / J.S. Matos, J.C. Ferreira, A.C. Leao and J.M. Silva -- Organization of the Test Bus for Analog and Mixed-Signal Systems / J.A. Starzyk, Z.H. Liu and J. Zou -- Designing Self-Exercising Analogue Checkers / V. Kolarik, M. Lubaszewski and B. Courtois -- Analog Circuit Observer Blocks / R. Harjani and B. Vinnakota -- FACTS: Fault Coverage Estimation by Test Vector Sampling / K. Heragu, V.D. Agrawal and M.L. Bushnell -- New Advances in Path Delay Fault Testing of Combinational Circuits / X. Xie and A. Albicki -- Realization of Fully Path-Delay-Fault Testable Non-Scan Sequential Circuits / W. Ke and P.R. Menon -- On Broad-Side Delay Test / J. Savir and S. Patil -- Weighted Random Robust Path Delay Testing of Synthesized Multilevel Circuits / W. Wang and S.K. Gupta -- Fault Models and Tests for Ring Address Type FIFOs / A.J. van de Goor, I. Schanstra and Y. Zorian -- Industrial Experience in the Built-in Self Test of Embedded RAMs / P. Camurati, P. Prinetto, M. Sonza Reorda, S. Barbagallo, A. Burri and D. Medina -- Automating the Verification of Memory Tests / A.J. van de Goor and B. Smit -- Automated Failure Analysis (AFA) Methodology for Repeated Structures / D.Y. Lepejian, J.M. Caywood, A. Kablanian, F.J. Ferguson and A. Jee -- Linear Finite State Machine for 1-D ILAs / M.M.R. Gala, P. Utama, D.E. Ross and K.L. Watson -- Functional Design Verification for the PowerPC 601 Microprocessor / S. Glenn, G. Meil, E. Rodriguez and J. Brooks -- Fault Probabilities in Routing Channels of VLSI Standard Cell Designs / G. Spiegel -- On Robustness of Required Random Test Length with Regard to Fault Occurrence Hypotheses / S. Crepaux, M. Jacomino and R. David
• Known-Good-Die Technologies on the Horizon / B. Vasquez, D. VanOverloop and S. Lindsey -- Analyzing the Design-For-Test Techniques in a Multiple Substrate MCM / J.A. Jorgenson and R.J. Wagner -- Analysis of I[subscript DDQ] Detectable Bridges in Combinational CMOS Circuits / E. Isern and J. Figueras -- Incorporating IDDQ Testing in BIST: Improved Coverage Through Test Diversity / A.D. Singh and J.P. Hurst -- Fault Detection and Fault Localization Using I[subscript DDQ]-Testing in Parallel Testable FAST-SRAMs / C. Elm and D. Tavangarian -- Circuit-Level Dictionaries of CMOS Bridging Faults / T. Lee, W. Chuang, I.N. Hajj and W.K. Fuchs -- CMOS Bridging Fault Modeling / M. Renovell, P. Huc and Y. Bertrand -- Eliminating Undetectable Shorts Between Horizontal Wires During Channel Routing / R. McGowen and F.J. Ferguson -- Design for Testability of On-Line Multipliers / H. Bederr, M. Nicolaidis and A. Guyot -- Boundary-Scan: Beyond Production Test / R.M. Sedmak -- New High Level Testability Measure: Description and Evaluation / M.H. Gentil, D. Crestani, A. El Rhalibi and C. Durante -- Impact of Behavioral Modifications for Testability / T. Thomas, P. Vishakantaiah and J.A. Abraham -- Open Faults in BiCMOS Gates / S.C. Ma and E.J. McCluskey -- Gate-to-Channel Shorts in BiCMOS Logic Gates / C.-J. Chen and S. Mourad -- On Evaluating Competing Bridge Fault Models for CMOS ICs / B. Chess, C. Roth and T. Larrabee -- Three-Pattern Tests for Delay Faults / P. Franco and E.J. McCluskey -- Input Pattern Classification for Transistor Level Testing of BiCMOS Circuits / S.M. Menon, A.P. Jayasumana and Y.K. Malaiya.

ISBN

• 0818654406
• 9780818654404
• 0818654422
• 9780818654428

LCCN

94075000

OCLC

• ocm31242541
• 31242541
• SCSB-2041846

Owning Institutions

Princeton University Library